DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election of claims 1-16 and newly added claims 21-24 in the reply filed on 03/19/26 is acknowledged. By this election, claims 17-20 are cancelled and claims 1-16 and 21-24 are pending in the application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 10, 12-13 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Onuki et al. (2018/0090498).
Regarding claims 1-2, Onuki (Figs. 1-19) discloses a semiconductor structure, comprising: a first interconnect structure (L1, L2, L3, L4) disposed over a first semiconductor substrate 300 (Fig. 14); and a thermal sensing device 17 comprising: a first transistor M11, M1 and a second transistor M10, M1, at least one selected from the group of the first and second transistors being embedded in the first interconnect structure (Figs. 1 and 14, [0079], [0082] and [0152]); a first capacitor Cs and a second capacitor Cs respectively coupled to the first transistor M1 and the second transistor M1 (Fig. 14, [0114]); and a metallization pattern 402 embedded in the first interconnect structure and serving as a resistive heater 400 (Figs. 1, 14 and 19, [0245]).
Regarding claim 3, Onuki (Figs. 1-19) discloses wherein the first transistor M1 is disposed over the first semiconductor substrate 300 and underneath the first interconnect structure, and the second transistor Tr1 is disposed over the first transistor M1 and embedded in the first interconnect structure (Fig. 14).
Regarding claim 10, Onuki (Figs. 1-19) discloses wherein the metallization pattern 400 is distributed at different levels of the first interconnect structure (Fig. 19).
Regarding claim 12, Onuki (Figs. 1-19) discloses a semiconductor structure, comprising: an interconnect structure (L1, L2, L3, L4) over a semiconductor substrate 300 (Fig. 14); and a thermal sensing device 17 comprising: a resistive component 400 embedded in the interconnect structure and serving as a heater (Figs. 1 and 18-19, [0079] and [0245]); and a filter component coupled to the resistive component 400 and allowing signals between a selected frequency range, the filter component comprising a transistor Tr1 and a capacitor Cs connected to the transistor Tr1 (Figs. 1, 14 and 19, [0154], [0245]).
Regarding claim 13, Onuki (Figs. 1-19) discloses wherein the transistor Tr1 of the filter component is embedded in the interconnect structure (L1, L2, L3, L4).
Regarding claim 16, Onuki (Fig. 16) discloses further comprising: a through via 332 penetrating through the interconnect structure L4 and the semiconductor substrate.
Allowable Subject Matter
Claims 4-9, 11 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record fails to disclose all the limitations recited in the above claims. Specifically, the prior art of record fails to disclose further comprising: a first bonding layer disposed on a topmost layer of the first interconnect structure, wherein at least a portion of the metallization pattern is embedded in the topmost layer of the first interconnect structure (claims 4 and 14); or wherein the first transistor and the first capacitor are included in a low-pass filter, the second transistor and the second capacitor are included in a high-pass filter (claim 11).
Claims 21-24 are allowed.
The following is an examiner's statement of reasons for allowance:
The prior art of record neither anticipates nor renders obvious all the limitations in the base claim 21. Specifically, the combination of a semiconductor structure, comprising: a first bonding layer disposed on the first interconnect structure; and a first thermal sensing device disposed between the first bonding layer and the first semiconductor substrate, the first thermal sensing device comprising: a resistive component comprising a first metallization pattern distributed at different levels of the first interconnect structure, the first metallization pattern comprising a metal line extending in a horizontal direction, a first conductive via disposed on a first side of the metal line and extending in a vertical direction, and a second conductive via disposed on a second side opposite to the first side and extending in the vertical direction, wherein a voltage is measured across the first conductive via and an oscillating current passes through the second conductive via.
The dependent claims being further limiting and definite are also allowable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THERESA T DOAN whose telephone number is (571)272-1704. The examiner can normally be reached on Monday, Tuesday, Wednesday and Thursday from 7:00AM - 3:00PM.
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/THERESA T DOAN/ Primary Examiner, Art Unit 2814
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