DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-18) in the reply filed on 04/16/2026 is acknowledged.
Claims 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/16/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-12 and 14-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2022/0165856 A1; hereinafter, “Yu”).
Regarding claims 1-12 and 14:
re claim 1, Yu discloses (in Fig. 15) a semiconductor structure comprising:
a first active area (e.g., the stack on the left side of Fig. 15 denoted by “300”) having first 226D and second 226S source-drain regions [0017];
a nanosheet region (e.g., channel 2080, [0015] and [0002], wherein the channel region may be nanosheets) of the active area interconnecting the first and second source-drain
regions;
a gate 250 (Fig. 2 and [0015]) overlying and surrounding the nanosheet region;
a direct backside contact (DBC) 280 [0032] located below the gate in the nanosheet region; and
a wrap-around dielectric liner 260/284 [0023] having horizontal portions (Fig. 15) and vertical portions, wherein the horizontal portions (of 260 in Fig. 15) contact the top [edge] of the direct backside contact (DBC) 280 (Fig. 15) and the vertical portions (of 284 in Fig. 15) contact sidewalls of the direct backside contact (DBC) 280 (Fig. 15);
re claim 2, the semiconductor structure of Claim 1, wherein the wrap-around material is selected from the group comprising SiCO, SiBCN SiCON, and Aluminum Oxide ([0032] wherein at least element 284 comprises aluminum oxide);
re claim 3, the semiconductor structure of Claim 1, further comprising:
a gate spacer 216 (Figs. 2, 15 and [0017]) on opposing verticals sides of the gate 250, wherein the gate spacer 216 [0017] and the wrap-around dielectric liner 260/284 [0023] are the same material (i.e., both 216 and 260 can be silicon nitride [0017 and 0023]);
re claim 4, the semiconductor structure of Claim 1, further comprising a back side power rail (BSPR) in contact with the direct backside contact (DBC) 280 ([0035], last sentence);
re claim 5, the semiconductor structure of Claim 1, wherein the direct backside contact (DBC) 280 (Fig. 15) contacts the second source-drain region 226S;
re claim 6, the semiconductor structure of Claim 5, wherein the vertical portion of wrap-around dielectric liner 260/284 (Fig. 15) is in [thermal] contact with sidewalls of the second source-drain 226S of the first active area and sidewalls of the direct backside contact (DBC) 280;
re claim 7, the semiconductor structure of Claim 5, further comprising a frontside contact 230 (on the left side of Fig. 15, note that “contact” does not require “electrical contact”) to the first source-drain region 226D (on the left side of Fig. 15) wherein the frontside contact does not overlay the direct backside contact (DBC) 280 (Fig. 15);
re claim 8, the semiconductor structure of Claim 1, further comprising:
a second active area (the stack on the right side of Fig. 15) having another source drain region 226D (on the right side of Fig. 15) and a second nanosheet region (e.g., channels 2080 in the left-side stack in Figs. 15 and 2) wherein the gate 250 (Fig. 2 and [0015]) overlies and surrounds the second nanosheet region;
a dielectric island 266 (Fig. 15 and [0027]) under the second nanosheet region;
wherein the wrap-around dielectric liner 260/284 is located on a top surface and a portion of the sidewalls of the dielectric island 266 (Fig. 15);
re claim 9, the semiconductor structure of Claim 8, wherein the vertical portion 284 (Fig. 5) of wrap-around dielectric liner 260/284 is in [thermal] contact with the other source-drain 226D (on the right side of Fig. 15);
re claim 10, the semiconductor structure of Claim 8, further comprising:
a placeholder material 264 (on the right side of Fig. 15) under the other source drain region 226D (on the right side of Fig. 15) wherein the vertical portion 284 of wrap-around dielectric liner 260/284 is in [thermal] contact with an upper portion of the sidewall placeholder
material 264;
re claim 11, the semiconductor structure of Claim 1, further comprising:
a shallow trench isolation (STI) region 204/270 (Figs. 2B-2D, 14B-14D and [0014 and 0030]) separating the first and second active regions (note the views in Figs. 14B-14D and Fig. 15 are orthogonal in the x, y directions) wherein the shallow trench isolation (STI) region comprises a shallow trench isolation (STI) liner 270 and a shallow trench isolation (STI) insulator 204;
wherein the shallow trench isolation (STI) liner 270 (Fig. 15) is located under the vertical portion 284 of the wrap-around dielectric liner 260/284 and [thermally] contacts sidewalls of the direct backside contact BCD 280;
re claim 12, the semiconductor structure of Claim 11, wherein the shallow trench isolation (STI) liner 270 (Fig. 15) and the vertical portion 284 of the wrap-around dielectric liner 260/284 have the same width (i.e., the current claim does not specify any particular dimension for the width; accordingly, any portion of either “270” could be chosen that has the same width as a chosen portion of “284”); and
re claim 14, the semiconductor structure of Claim 11, wherein the vertical portion 284 (Fig. 15) of the wrap-around dielectric liner 260/284 is from about 1% to about 50% [in thickness] of a [width from] sidewall [to sidewall] of the direct backside contact BCD 280 (Fig. 15).
Therefore, Yu anticipates claims 1-12 and 14.
Regarding claims 15-18:
re claim 15, Yu discloses (in Fig. 15) a semiconductor structure comprising:
a first active area and a second active area (e.g., the two stacks “300” in Fig. 15) each having first and second source-drain regions 226D/226S/226D (as shown in Fig. 15);
a shallow trench isolation (STI) region 204 (Figs. 2B-2D, 14B-14D and [0014]) separating the first and second active areas (e.g., in the “x” direction of Figs. 14B-14D and 15);
a nanosheet region 2080 (Fig. 15 and [0015]) in each active area interconnecting the first and second source-drain regions 226D/226S of each active area;
a gate structure 250 (Fig. 2 and [0015]) over the nanosheet region of each of the first and second active areas and the shallow trench isolation region (Note: “shallow trench” should be inserted to avoid indefiniteness);
a dielectric island 266 (Figs. 14D, 15 and [0027]) adjacent the shallow trench isolation (STI) region 204 and under the nanosheet region of the second active area (Fig. 15), the dielectric island 266 having an upper portion;
a direct backside contact (DBC) 280 (Fig. 15 and [0032]) located below the nanosheet region and the second source-drain region 226S (Fig. 15) of the first active area (e.g., the left stack 300 in Fig. 15), the direct backside contact (DBC) 280 having an upper portion in [thermal] contact with the second source-drain region 226S of the first active area;
a power rail in contact with a lower portion of the direct backside contact (DBC) 280 ([0035], last sentence); and
a wrap-around dielectric liner 260/284 (Fig. 15) wrapping the upper portion of the direct backside contact (DBC) 280 (Fig. 15) under the nanosheet region of the first active area and the upper portion of the dielectric island 266 (Fig. 15);
re claim 16, the semiconductor structure of Claim 15, wherein the wrap-around dielectric liner 260/284 (Fig. 15) has a vertical portion 284 in [thermal] contact with the second source-drain 226D (on the left side of Fig. 15) of the first active area region and the direct backside contact (DBC) 280;
re claim 17, the semiconductor structure of Claim 15, wherein the wrap-around dielectric liner 260/284 has a vertical portion 284 in [thermal contact with the second source-drain 226D (on the right side of Fig. 15) of the second active area region; and
re claim 18, the semiconductor structure of Claim 17, wherein the vertical portion 284 of the wrap-around dielectric liner 260/284 (Fig. 15) is in [thermal] contact with a placeholder material 264 (on the right side of Fig. 15) located under the second source-drain 226D (on the right side of Fig. 15) of the second active area region.
Therefore, Yu anticipates claims 15-18.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu.
Yu anticipates claims 11 and discloses the liner STI liner 270 and the wrap around dielectric liner 260/284 can be various different materials [0030 and 0032]; however, Yu does not explicitly disclose the shallow trench isolation (STI) liner 270 and the wrap-around dielectric liner are different materials. However, the current claim is deemed obvious because the general conditions of the claimed invention are disclosed, and given Yu, one of ordinary skill in the art would have ready recognized that different material could be specifically chosen from the list of materials disclosed by Yu, especially to provide etch selectivity such that openings, trenches, patterns, etc. can be accurately formed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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