Prosecution Insights
Last updated: July 17, 2026
Application No. 18/533,161

DRIVING SYSTEM FOR SWITCHING DEVICE

Final Rejection §102§103
Filed
Dec 07, 2023
Priority
Jan 03, 2023 — CN 202310003679.9
Examiner
CHEN, PATRICK C
Art Unit
2842
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Delta Electronics (Shanghai) Co., Ltd.
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
472 granted / 573 resolved
+14.4% vs TC avg
Moderate +9% lift
Without
With
+9.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
34 currently pending
Career history
614
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
79.3%
+39.3% vs TC avg
§102
14.6%
-25.4% vs TC avg
§112
3.4%
-36.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 573 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. In addressing the rejection ground, each claim may not have been separately discussed to the extent the claimed features are the same as or similar to the previously-discussed features; the previous discussion is construed to apply for the other claims in the same or similar way. In the office action, “/” should be read as and/or as generally understood. For example, “A/B” means A and B, or A or B. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-2, 10, 12, and 14-17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nosaka et al. (US 2023/0387912). Regarding claim 1, Nosaka discloses a driving system [see at least fig. 22, 26, 28, 29] for driving at least one switching device, comprising: at least one switch driving module [the circuits in between Vout and Q] receiving a driving signal [e.g. Vout] and outputting a driving voltage [e.g. the gate control voltage of Q] according to the driving signal; and at least one switching device [e.g. Q] electrically coupled to the at least one switch driving module, wherein the switching device receives the driving voltage, and the switching device is turned on or off according to the driving voltage, wherein the switch driving module comprises: a high-impedance voltage dividing module [e.g. Rp, Dt, Rt, Cp/Rgon,Dp,Rgoff], wherein the high-impedance voltage dividing module is configured for dividing and limiting the driving voltage of the switching device when the switching device is turned on, thereby making a gate-source voltage of the switching device to be lower than a clamping voltage value [e.g. Df, Rf/Dg,ZDg]; and a constant voltage dividing module [e.g. Rs, Cs/21] electrically coupled to the high-impedance voltage dividing module, wherein when the switching device is turned off and the changing rate of a drain-source voltage of the switching device is too high, the constant voltage dividing module provides a low-impedance shunt path [e.g. Qs is turned on] for the gate-source of the switching device to make the gate-source voltage of the switching device to be lower than a trigger threshold [e.g. the threshold of Q]. Regarding claim 2, Nosaka discloses the driving system according to claim 1, further comprising: a control module [e.g. the circuit (not shown) that generates Vsig] configured for outputting a control signal [e.g. Vsig]; and a driving pulse generating module [ see at least 10 fig. 3/ the circuit that receives Vsig and outputs the gate control signal] electrically coupled to the control module and the switch driving module, wherein the driving pulse generating module receives the control signal and outputs the driving signal to the switch driving module according to the control signal. Regarding claim 10, Nosaka discloses the driving system according to claim 1, wherein the switch driving module further comprises a voltage clamping module [e.g. Dg, ZDg/Df, Rf] electrically coupled to the constant voltage dividing module and a source of the switching device and configured for clamping the gate-source voltage of the switching device. Regarding claim 12, Nosaka discloses the driving system according to claim 1, wherein when the switching device is turned off, the constant voltage dividing module clamps the gate-source voltage of the switching device to a low constant negative voltage value [see at least paras. 0002-0005, 0008] for providing a turn-off path for the switching device and reducing the reverse conduction voltage of the switching device. Regarding claim 14, Nosaka discloses the driving system according to claim 1, wherein the at least one switching device comprises a first switching device and a second switching device, wherein the first switching device and the second switching device are electrically coupled in series to form a half-bridge switching circuit [see at least fig. 1A]. Regarding claim 15, Nosaka discloses a driving system for driving at least one switching device, comprising: at least one switch driving module receiving a driving signal and outputting a driving voltage according to the driving signal; and at least one switching device electrically coupled to the at least one switch driving module, wherein the switching device receives the driving voltage, and the switching device is turned on or off according to the driving voltage, wherein the switch driving module comprises: a high-impedance voltage dividing module, wherein the high-impedance voltage dividing module is configured for dividing and limiting the driving voltage of the switching device when the switching device is turned on, thereby making a gate-source voltage of the switching device to be lower than a clamping voltage value; and a constant voltage dividing module electrically coupled to the high-impedance voltage dividing module, wherein when the switching device is turned off, the constant voltage dividing module clamps the gate-source voltage of the switching device to a low constant negative voltage value for providing a turn-off path for the switching device and reducing the reverse conduction voltage of the switching device. See at least rejection of claim 1. Regarding claim 16, Nosaka discloses the driving system according to claim 15, wherein the switch driving module further comprises a voltage clamping module [e.g. Dg, ZDg/Df, Rf] electrically coupled to the constant voltage dividing module and a source of the switching device and configured for clamping the gate-source voltage of the switching device. Regarding claim 17, Nosaka discloses the driving system according to claim 15, further comprising: a control module configured for outputting a control signal; and a driving pulse generating module electrically coupled to the control module and the switch driving module, wherein the driving pulse generating module comprises a driving chip which receives the control signal and outputs the driving signal to the switch driving module according to the control signal. See at least rejection of claim 2. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nosaka et al. (US 2023/0387912) in view of Chuang (US 2021/0226621). Regarding claim 11, Nosaka discloses the driving system according to claim 10, except wherein the voltage clamping module comprises a second Zener diode and a third Zener diode electrically coupled in series, an anode of the second Zener diode is electrically coupled to an anode of the third Zener diode, a cathode of the second Zener diode is electrically coupled to a gate of the switching device, a cathode of the third Zener diode is electrically coupled to the source of the switching device. However, Chuang discloses a voltage clamping module comprises a second Zener diode [e.g. Z3 fig. 15] and a third Zener diode [e.g. Z4 fig. 15] electrically coupled in series, an anode of the second Zener diode is electrically coupled to an anode of the third Zener diode, a cathode of the second Zener diode is electrically coupled to a gate of the switching device, a cathode of the third Zener diode is electrically coupled to the source of the switching device [also see fig. 9]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Nosaka in accordance with the teaching of Chuang regarding a voltage clamp in order to provide an alternative clamp circuit [paras. 0117-0129]. Claim 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nosaka et al. (US 2023/0387912) in view of Arisawa et al. (US 2020/0395933). Regarding claim 13, Nosaka discloses the driving system according to claim 1, except wherein the switching device is a GaN device. However, Arisawa discloses the advantage of a GaN device [ para. 0050]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Nosaka in accordance with the teaching of Arisawa regarding a GaN device in order to provide a transistor that achieves normally-off operation with high current and low on-resistance [para. 0050]. Claim 3-5 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nosaka et al. (US 2023/0387912) in view of Qu et al. (US 2024/0178831). Regarding claim 3, Nosaka discloses the driving system according to claim 2, wherein the driving pulse generating module receives the control signal and outputs the driving signal. Nosaka does not disclose the driving pulse generating module comprises a driving chip. However, Qu discloses a driving pulse generating module comprises a driving chip [see at least integrated gate driver fig. 2/3/6/8, paras. 0075, 0085, 0091]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Nosaka in accordance with the teaching of Qu regarding a gate driver in order to utilize a gate driver chip to drive a switching device. Regarding claim 4, the combination discussed above discloses the driving system according to claim 3, wherein the high-impedance voltage dividing module comprises a first capacitor [e.g. Cp] and a first resistor [e.g. Rt] electrically coupled in parallel, a first terminal [e.g. the left/right terminal] of the first capacitor and a first terminal [e.g. the left/right terminal] of the first resistor are both electrically coupled to a first node [e.g. the node between Cs and Cp/between Cs and G], a second terminal of the first capacitor and a second terminal of the first resistor are both electrically coupled to a second node [e.g. the node between Cp and Rgon/between Cs and Cp], the first node and the second node are electrically coupled to the driving chip through two driving resistors [e.g. R1, R2 fig. 2 of Qu, Rp, Rgon/Rs, Rp/Rp, Rgoff Nosaka] respectively. Regarding claim 5, the combination discussed above discloses the driving system according to claim 4, wherein the first node is electrically coupled to a first output terminal of the driving chip, and the second node is electrically coupled to a second output terminal of the driving chip, wherein the voltage level of the first output terminal is higher than that of the second output terminal [see at least fig. 2 of Qu]. Regarding claim 18, the combination discussed in claim 4 discloses the driving system according to claim 17, wherein the high-impedance voltage dividing module comprises a first capacitor and a first resistor electrically coupled in parallel, a first terminal of the first capacitor and a first terminal of the first resistor are both electrically coupled to a first node, a second terminal of the first capacitor and a second terminal of the first resistor are both electrically coupled to a second node, the first node and the second node are electrically coupled to the driving chip through two driving resistors respectively. See rejection of claim 4. Allowable Subject Matter Claims 8-9 and 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant's arguments filed 10/23/2025 have been fully considered but they are not persuasive. Applicant argues: ‘Paragraph [0018] of Applicant's specification discloses the feature "In an embodiment, when the switching device 3 is turned off, the constant voltage dividing module 22 clamps the gate-source driving voltage of the switching device 3 to a low constant negative voltage value for providing a turn-off path for the switching device 3 and reducing the reverse conduction voltage of the switching device 3. In an embodiment, the driving system 1 includes two switching devices 3, the two switching devices 3 are electrically coupled in series to form a half-bridge switching circuit". Namely, the constant voltage dividing module 22 clamps the gate-source driving voltage to a low constant negative voltage value. The low constant negative voltage value is constant. The low constant negative voltage value has the advantages of preventing an excessive reverse conduction voltage that may break down and cause damage to the switching device, and reducing the reverse conduction loss. According to Figure 22 of Nosaka, the module which the Office considers to be the constant voltage dividing module 22 of the presently claimed invention, is composed of the resistor Rs and the capacitor Cs. Moreover, according to the Figure 15 of Nosaka, the voltage of the capacitor Cs (i.e., the voltage Vcs) is variable but not constant. Namely, the voltage of the Nosaka's module regarded as the constant voltage dividing module 22 is variable and not constant. The control stability and the technical effect of the module of Nosaka are reduced. Hence, Nosaka does not disclose the features "a constant voltage dividing module electrically coupled to the high-impedance voltage dividing module, wherein when the switching device is turned off and the changing rate of a drain-source voltage of the switching device is too high, the constant voltage dividing module provides a low-impedance shunt path for the gate-source of the switching device to make the gate-source voltage of the switching device to be lower than a trigger threshold" as recited in Claim 1 and the features "a constant voltage dividing module electrically coupled to the high-impedance voltage dividing module, wherein when the switching device is turned off, the constant voltage dividing module clamps the gate-source voltage of the switching device to a low constant negative voltage value for providing a turn-off path for the switching device and reducing the reverse conduction voltage of the switching device" as recited in Claim 15.’ However, claims 1 does not recite “a low constant negative voltage value”. Therefore, “a low constant negative voltage value” is not a limitation for claim 1. Assuming arguendo, “a low constant negative voltage value” is a limitation for claim 1, at least fig. 21 shows the gate-source voltage of the switching device is a low constant negative voltage value. In addition, Nosaka discloses a constant voltage dividing module [e.g. Rs, Cs/21] electrically coupled to the high-impedance voltage dividing module, wherein when the switching device is turned off and the changing rate of a drain-source voltage of the switching device is too high, the constant voltage dividing module provides a low-impedance shunt path [e.g. Qs is turned on] for the gate-source of the switching device to make the gate-source voltage of the switching device to be lower than a trigger threshold [e.g. the threshold of Q]. Regarding claim 15, Nosaka discloses a constant voltage dividing module e.g. Rs, Cs/21] electrically coupled to the high-impedance voltage dividing module, wherein when the switching device is turned off, the constant voltage dividing module clamps the gate-source voltage of the switching device to a low constant negative voltage value [see at least fig. 21] for providing a turn-off path for the switching device and reducing the reverse conduction voltage of the switching device Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICK C CHEN whose telephone number is (571)270-7207. The examiner can normally be reached M-F Flexible 8:00-16:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICK C CHEN/Primary Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Dec 07, 2023
Application Filed
Jul 28, 2025
Non-Final Rejection mailed — §102, §103
Oct 23, 2025
Response Filed
Jun 18, 2026
Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
92%
With Interview (+9.4%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 573 resolved cases by this examiner. Grant probability derived from career allowance rate.

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