Prosecution Insights
Last updated: April 19, 2026
Application No. 18/533,172

SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CONTROLLING ROW HAMMERING AND METHOD OF DRIVING THE SAME

Final Rejection §102
Filed
Dec 08, 2023
Examiner
HOANG, HUAN
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK Hynix Inc.
OA Round
2 (Final)
93%
Grant Probability
Favorable
3-4
OA Rounds
1y 11m
To Grant
99%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allow Rate
1123 granted / 1206 resolved
+25.1% vs TC avg
Moderate +6% lift
Without
With
+5.7%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
21 currently pending
Career history
1227
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
24.6%
-15.4% vs TC avg
§102
34.5%
-5.5% vs TC avg
§112
19.2%
-20.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1206 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The Amendment filed on 10/28/2025 has been received and entered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 7-14 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2016/0064056, hereinafter “Kim”). Regarding claims 7 and 18, Kim (Fig. 16) shows a method of driving a semiconductor memory device, the method comprising: applying a driving voltage (VPP) to a selected word line (WL2) among a plurality of word lines; applying an off voltage to remaining non-selected word lines (Abstract, lines 8-10 and WL1 and WL3); and applying a victim voltage (VBB21), which is different from the off voltage, to a word line adjacent to the selected word line among the non-selected word lines during a falling section where a voltage of the selected word line is transited from the driving voltage to the off voltage (from VPP to VSS), wherein a voltage level of the victim voltage is lower than a voltage level of the off voltage. Regarding claim 8, Kim (Fig. 16) shows the method of claim 7, wherein the driving voltage comprises a voltage having a logic high level (VPP), and the off voltage comprises a ground voltage (VSS and Abstract, lines 10-11). Regarding claim 9, Kim (Fig. 16) shows the method of claim 7, wherein the selected word line comprises an nth word line among the word lines, and the victim word line comprises at least one of a (n±1)th word lines to a (n±a)th word line, where a is a natural number, among the word lines. Regarding claim 11, Kim (Fig. 16) shows a method of driving a semiconductor memory device, the method comprising: setting a victim word line (Wl1 or WL3) from address information of an aggressor word line (the WL1 and WL3 are identified as adjacent word lines by the address of WL2); and applying a victim voltage (negative volage VBB21), which is lower than different from an off voltage (Abstract, lines 8-11, ground voltage), to the victim word line during a falling section of the aggressor word line (t22, word line WL2 from VPP to VSS). Regarding claim 12, Kim discloses the method of claim 11, wherein the address information of the aggressor word line comprises address information of a selected word line among the word lines (paragraph [0083], lines 9-11). Regarding claim 13, Kim discloses the method of claim 12, wherein the victim word line comprises at least one of word lines adjacent to the selected word line. Regarding claims 10 and 19, Kim (Fig. 16) shows the method of claim 7 and the method of claim 11, wherein the falling section is delayed from a falling edge where the driving voltage is transited to the off voltage (the delay is the time from VPP to VSS). Regarding claims 14 and 20, Kim (Fig. 16) shows the method of claim 12, further comprising: applying a driving voltage having a logic high level (VPP) to the aggressor word line during an enable section of the aggressor word line; and applying the off voltage having a logic low level (ground or VBB21) to a-non-selected word lines among the word lines. Response to Arguments Applicant’s arguments with respect to claims 7-14 and 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUAN HOANG whose telephone number is (571)272-1779. The examiner can normally be reached 7:30AM-4:00PM M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HUAN HOANG/Primary Examiner, Art Unit 2827
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Prosecution Timeline

Dec 08, 2023
Application Filed
Jul 24, 2025
Non-Final Rejection — §102
Oct 28, 2025
Response Filed
Feb 06, 2026
Final Rejection — §102
Apr 06, 2026
Applicant Interview (Telephonic)
Apr 06, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603116
OPERATING METHOD OF MEMORY CONTROLLER, AND MEMORY DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12597462
NON-VOLATILE MEMORY WITH HYBRID ROUTING FOR SHARED WORD LINE SWITCHES
2y 5m to grant Granted Apr 07, 2026
Patent 12592277
DISTRIBUTED WRITE DRIVER FOR MEMORY ARRAY
2y 5m to grant Granted Mar 31, 2026
Patent 12592278
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
2y 5m to grant Granted Mar 31, 2026
Patent 12586630
MEMORY ARRAY CIRCUIT
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
93%
Grant Probability
99%
With Interview (+5.7%)
1y 11m
Median Time to Grant
Moderate
PTA Risk
Based on 1206 resolved cases by this examiner. Grant probability derived from career allow rate.

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