DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
An English language translation of the non-English language foreign application has not been received.
Status of Claims
Claims 1-10 are pending.
Claims 1-10 are original.
Claims 1-5 and 9-10 are rejected herein.
Claims 6-8 are objected to herein.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE INCLUDING T-COIL AND CAPACITOR CONNECTED BETWEEN POWER LINES.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 9 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Daley (US 20090322446 A1).
Regarding claim 9, Daley discloses (see generally, e.g., FIGS. 1-3A):
A semiconductor device (10) comprising:
a T-coil including an inductor (20) having a spiral shape (see, e.g., FIG. 1);
at least one capacitor (16) including a dielectric layer (12, 14) patterned into a plurality of rectangular shapes with a longest side perpendicular to an extension direction of the inductor (20) and located below the T-coil (see, e.g., FIGS 1 and 2A); and
a first power line and a second power line that are electrically connected to the at least one capacitor (16) (see, e.g., paragraph [0030] – “[p]ort 25 of the on-chip capacitor 16 is connected to a power supply terminal of one polarity and port 35 of the on-chip capacitor 16 is connected to the power supply terminal of opposite polarity” – the disclosed connections to the power supply terminals read on the claimed first and second power lines).
Note, the capacitor 16 is embedded in the dielectric layers 12 and 14 (see, e.g., FIGS. 2A). Accordingly, the electrodes 30, 32, 38, 40 of the capacitor 16 (see, e.g., FIG. 2) divide and/or pattern the dielectric layers 12 and 14 into a plurality of rectangular shapes, e.g., the rectangular shapes between laterally adjacent ones of the electrodes.
Note also, the longest sides of the rectangular shapes (i.e., along the X-direction) are perpendicular to an extension direction (i.e., the Y-direction) of the inductor (20). See, e.g., annotated FIG. 1 herein.
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ANNOTATED FIG. 1 OF DALEY
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong (US 20250047097 A1) in view of Daley.
Regarding claim 1, Jeong disclose (see generally, e.g., FIGS. 1 and 5):
A semiconductor device (10) comprising:
a T-coil (L1, L2) transferring a signal from the outside (i.e., from I/O pad 100) to an internal circuit (600);
a plurality of power lines (e.g., the lines between the VDD and VSS pads 400 and 500 and the internal circuit 600) transferring power from the outside (i.e., from pads 400 and 500) to the internal circuit (600).
Jeong does not explicitly disclose the plurality of power lines disposed below the T-coil; and
at least one capacitor connected between the plurality of power lines.
However, in analogous art, Daley discloses:
the plurality of power lines disposed below a T-coil (20); and
at least one capacitor (16) connected between the plurality of power lines.
Note, Daley discloses “[p]ort 25 of the on-chip capacitor 16 is connected to a power supply terminal of one polarity and port 35 of the on-chip capacitor 16 is connected to the power supply terminal of opposite polarity.” Paragraph [0030]. The disclosed connections to the power supply terminals read on the claimed plurality of power lines. Daley also discloses “[c]onductive features in the different metallization levels of the BEOL wiring structure, such as the representative features 13, 15, 17 visible in FIG. 2A, interconnect devices of an integrated circuit and may provide circuit-to-circuit connections, or may establish contacts with input and output terminals.” Paragraph [0022]. As shown in FIG. 2A, the feature 13 is below the spiral shaped inductor 20. Moreover, Daley discloses that the capacitor 16 is below the spiral shaped inductor (20). See, e.g., FIG. 2A. Accordingly, insomuch as the capacitor 16 is below the spiral shaped inductor (20), the connections to the capacitor 16 (i.e., the connections to the power supply terminals reading on the claimed first and second power lines) must also be (at least partially) below the spiral shaped inductor (20), e.g., like feature 13 which is explicitly disclosed as establishing contacts with terminals (i.e., such as the power supply terminals disclosed in paragraph [0030]).
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have made the semiconductor device (10) of Jeong with the plurality of power supply lines disposed below the T-coil and at least one capacitor connected between the plurality of power supply lines as taught by Daley according to known methods to yield predictable results, for example, so that the capacitor can decouple the power supply lines, suppress high-frequency noise in the power supply signals, shunt high-frequency noise to ground, reduce voltage ripple and/or otherwise stabilize the power supply lines.
Regarding claim 2, Jeong in view of Daley as applied to claim 1 discloses the semiconductor device of claim 1.
Jeong further discloses:
wherein the plurality of power lines include a first power line (i.e., the line between the VDD pad 400 and the internal circuit 600) and a second power line (i.e., the line between the VSS pad 500 and the internal circuit 600),
the first power line transfers an external voltage (i.e., a power voltage VDD – see, e.g., paragraph [0025]), and
the second power line transfers a ground voltage (i.e., a ground voltage VSS – see, e.g., paragraph [0025]).
Regarding claim 3, Jeong in view of Daley as applied to claim 2 discloses the semiconductor device of claim 2.
While Jeong discloses that the T-coil (L1, L2) includes an inductor (L1), Jeong does not explicitly disclose that the inductor is patterned in a spiral shape.
However, in analogous art, Daley discloses the inductor (20) patterned in a spiral shape (see, e.g., FIG. 1).
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have patterned the inductor (L1) of Jeong in a spiral shape as taught by Daley according to known methods to yield predictable results, for example, so that the inductor has a low profile and is compact.
Regarding claim 4, Jeong in view of Daley as applied to claim 3 discloses the semiconductor device of claim 3.
Daley further discloses:
wherein the at least one capacitor (16) comprises:
a dielectric layer (12) formed on a first conductive layer (40),
a second conductive layer (32) formed on the dielectric layer (12),
a third conductive layer (28) formed at the same layer as the second conductive layer (32). See, e.g., FIG. 2A.
Regarding claim 5, Jeong in view of Daley as applied to claim 4 discloses the semiconductor device of claim 4.
Daley further discloses:
wherein the dielectric layer (12) is patterned into a plurality of rectangular shapes, and
is patterned so that a longest side of a rectangle is perpendicular to an extension direction of the inductor (20).
Note, the capacitor 16 is embedded in the dielectric layer 12 (see, e.g., FIGS. 2A). Accordingly, the electrodes 30 and 32 of the capacitor 16 (see, e.g., FIG. 2) divide and/or pattern the dielectric layer 12 into a plurality of rectangular shapes, e.g., the rectangular shapes between laterally adjacent ones of the electrodes.
Note also, the longest sides of the rectangular shapes (i.e., along the X-direction) are perpendicular to an extension direction (i.e., the Y-direction) of the inductor (20). See, e.g., annotated FIG. 1 herein.
Claim 10 is rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Daley.
Regarding claim 10, Daley as applied to claim 9 above discloses the semiconductor device (10) of claim 9.
Daley further discloses wherein one of the first power line and the second power line is located on the dielectric layer (12, 14).
Note, Daley discloses “[p]ort 25 of the on-chip capacitor 16 is connected to a power supply terminal of one polarity and port 35 of the on-chip capacitor 16 is connected to the power supply terminal of opposite polarity.” Paragraph [0030]. The disclosed connections to the power supply terminals read on the claimed first and second power lines. Daley also discloses “[c]onductive features in the different metallization levels of the BEOL wiring structure, such as the representative features 13, 15, 17 visible in FIG. 2A, interconnect devices of an integrated circuit and may provide circuit-to-circuit connections, or may establish contacts with input and output terminals.” Paragraph [0022]. As shown in FIG. 2A, the features 13, 15 and 17 are all on the dielectric layer (12, 14). Moreover, Daley discloses that the capacitor 16 is on the dielectric layers 12 and 14. See, e.g., FIG. 2A. Accordingly, insomuch as the capacitor 16 is on the dielectric layers 12 and 14, the connections to the capacitor 16 (i.e., the connections to the power supply terminals reading on the claimed first and second power lines) must also be (at least partially) on the dielectric layers 12 and 14, e.g., like features 13, 15 and 17 which are explicitly disclosed as establishing contacts with terminals (i.e., such as the power supply terminals disclosed in paragraph [0030]).
Alternatively, if deemed that Daley does not explicitly or inherently disclose that one of the first power line and the second power line is located on the dielectric layer, it would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have made the semiconductor device (10) of Daley with one of the first power line and the second power line located on the dielectric layer according to known methods to yield predictable results, e.g., to readily connect the power line to the capacitor (16) which is also on the dielectric layer (12, 14).
Again, Daley explicitly discloses “[c]onductive features in the different metallization levels of the BEOL wiring structure, such as the representative features 13, 15, 17 visible in FIG. 2A, interconnect devices of an integrated circuit and may provide circuit-to-circuit connections, or may establish contacts with input and output terminals.” Paragraph [0022]. As shown in FIG. 2A, the features 13, 15 and 17 are all on the dielectric layer (12, 14). It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used one of more of the features (13, 15, 17) of Daley as one of the first or second power lines according to known methods to yield predictable results, e.g., to connect the the capacitor (16) to the respective power supply terminals referenced in paragraph [0030]. In this way, the conductive features (13, 15, 17) are used (as explicitly disclosed in paragraph [0022] of Daley) for their intended purpose of making contact with various terminals.
Allowable Subject Matter
Claims 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 6, the prior art of record, alone or in combination, fails to disclose, along with the other claimed limitations and/or features, inter alia: “wherein an insulating layer is formed between the first conductive layer and the dielectric layer, between the dielectric layer and the second conductive layer, and between the first conductive layer and the third conductive layer,” in such a manner as to anticipate the claim or render the claim obvious.
Claims 7-8 depend from claim 6, and accordingly are indicated as including allowable subject matter for at least the same reasons as claim 6.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P CORNELY whose telephone number is (571)272-4172. The examiner can normally be reached Monday - Thursday 8:30 AM - 4:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOHN P. CORNELY
Examiner
Art Unit 2812
/J.P.C./Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812