Prosecution Insights
Last updated: August 17, 2026
Application No. 18/533,234

PRINTED CIRCUIT BOARD ASSEMBLY WITH REDUCED TOTAL HEIGHT

Final Rejection §103
Filed
Dec 08, 2023
Priority
Dec 12, 2022 — provisional 63/386,924
Examiner
SPRENGER, JAIME LYNN
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
MediaTek Inc.
OA Round
2 (Final)
100%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allowance Rate
1 granted / 1 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
23 currently pending
Career history
24
Total Applications
across all art units

Statute-Specific Performance

§103
52.0%
+12.0% vs TC avg
§102
26.7%
-13.3% vs TC avg
§112
16.0%
-24.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Examiner acknowledges the cancelation of Claims 1-10 in the remarks filed on 05/19/2026. Applicant’s arguments, see Remarks, filed 05-19-2026, with respect to Claim 19 have been fully considered and are persuasive. The 35 U.S.C §112 of Claim 19 has been withdrawn. The remainder of Applicant's arguments filed 05-19-2026 have been fully considered but they are not persuasive. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e.,” wherein the heat sink is physically separated and spaced apart from a vertical sidewall of the substrate.”) are not recited in the rejected claim(s). However, the features are taught by the reference of Mokler in Figure 1a and this rejection and reasoning is further discussed in the rejection of Claim 11 below. Therefore, the argument is found unpersuasive. In response to applicants’ argument that the combination of the cavity and the through-hole structure would not have been obvious examiner disagrees for the following reasons. Examiner stated in the rejection of Claim 11 in the Non-final rejection filed 02/24/2026 that the addition of the cavity “as described in Lee [is obvious] because adding this cavity to Mokler allows for the reduction of the overall thickness of the device.” By ‘adding this cavity to Mokler’ examiner did not modify the through-hole. But instead Mokler teaches the through-hole in a PNG media_image1.png 259 788 media_image1.png Greyscale package and Lee teaches putting a package in a cavity to reduce the overall thickness. The modification would look like something along the lines of my diagram depiction above (Lee Fig 18, Mokler Fig 1a). This further clarification of the previous rejection demonstrates that the modified device would indeed be obvious in light of the previously relied upon teachings. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 11-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Scott Mokler et al. (US 10548249 B2) herein after referred to as Mokler, and further in view of Soo Min Lee et al. (US 20250048557 A1) herein after referred to as Lee. Regarding Claim 11 Mokler teaches A printed circuit board assembly (100), comprising: (Fig. 1a and 4) a substrate (102) having a first surface (118) and a second surface (116) opposite to the first surface, wherein the substrate has a first thickness (132) ; a Chip mounting region (134) a plurality of bonding pads (122-2) a chip module (150) electrically connected to the substrate through the plurality of bonding pads. a through hole (112) disposed in the chip module mounting region (134) of the substrate (102); and a heat sink (120) disposed in the through hole and thermally coupled to the chip module. (Fig 4 element 144 Col. 7 lines 18-41) wherein the heat sink (120) is physically separated and spaced apart from a vertical sidewall of the substrate (102). (Fig 1a the hole 112 teaches that there is a physical separation) Mokler does not teach: a cavity disposed within a chip module mounting region of the substrate on the first surface that caves in towards the second surface, wherein the chip module mounting region of the substrate has a second thickness, wherein the second thickness is smaller than the first thickness; a plurality of bonding pads in the cavity; and a chip module mounted in the cavity and electrically connected to the substrate through the plurality of bonding pads. Lee teaches: a cavity (fig 1 and 18 element 150) disposed within a chip module mounting region of the substrate on the first surface (upper surface near 142) that caves in towards the second surface (lower surface near141), wherein the chip module mounting region of the substrate has a second thickness (thickness of substrate including 111 and below), wherein the second thickness is smaller than the first thickness (this first thickness would be whole thickness from first surface to second surface); a plurality of bonding pads (121p) in the cavity; and a chip module (920) mounted in the cavity and electrically connected to the substrate through the plurality of bonding pads. PNG media_image1.png 259 788 media_image1.png Greyscale It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Mokler such that the device has a cavity disposed within a chip module mounting region of the substrate on the first surface that caves in towards the second surface, wherein the chip module mounting region of the substrate has a second thickness, wherein the second thickness is smaller than the first thickness; a plurality of bonding pads in the cavity; and a chip module mounted in the cavity and electrically connected to the substrate through the plurality of bonding pads, as described in Lee because adding this cavity to Mokler allows for the reduction of the overall thickness of the device. (Lee, Para. [0009]) Regarding claim 12 Mokler in view of Lee teaches: The printed circuit board assembly according to claim 11, Mokler further teaches: wherein the chip module (150) is a multi-chip (110) module.(Fig. 4, Col. 5 lines 10-31) Regarding claim 13 Mokler in view of Lee teaches: The printed circuit board assembly according to claim 12, Mokler further teaches: wherein the multi-chip module (150) comprises a module board (106) having a third surface (126) directly facing the first surface (118) of the substrate (102), and a fourth surface (128) opposite to the third surface.(Fig. 4) Regarding claim 14 Mokler in view of Lee teaches: The printed circuit board assembly according to claim 13, Mokler further teaches: wherein the multi-chip module (150) further comprises a plurality of integrated circuit chips (110) mounted on the fourth surface (128) through a plurality of first ball grid array (BGA) balls.(Fig. 4 element114) Regarding claim 15 Mokler in view of Lee teaches: The printed circuit board assembly according to claim 14, Mokler further teaches: wherein the module board is mounted on the plurality of bonding pads (122-2) through a plurality of second ball grid array (BGA) balls.(Fig. 4 element 104) Regarding claim 16 Mokler in view of Lee teaches: The printed circuit board assembly according to claim 15, Mokler further teaches: wherein the first BGA balls (114) have a first width and the second BGA balls (104) have a second width, wherein the second width is greater than the first width. (Fig. 4 104 is wider than 114) Regarding claim 17 Mokler in view of Lee teaches: The printed circuit board assembly according to claim 16, Mokler further teaches: PNG media_image2.png 294 752 media_image2.png Greyscale wherein the first width (114) is about 0.2 mm and the second width (104) is about 0.63 mm. (Col. 5-6 lines 55-15 , element 136, the through hole width, highlighted by the arrow below, can be 3mm wide meaning the relative size of the first and second width can be assumed to be 0.2mm and 0.63mm respectively) Regarding claim 18 Mokler in view of Lee teaches: The printed circuit board assembly according to claim 13, Mokler further teaches: wherein the multi-chip module further comprises a plurality of capacitors (108) mounted on the third surface(126) of the module board(106). (Fig.4 Col. 4-5 lines 29-9) Regarding claim 19 Mokler in view of Lee teaches: The printed circuit board assembly according to claim 18, Mokler further teaches: PNG media_image2.png 294 752 media_image2.png Greyscale wherein the plurality of capacitors (108) have a thickness that is greater than or equal to 0.2 mm. (Fig. 1a and 4 Col. 4-5 lines 29-9, Col 5-6 lines 55-15 see below 108 is larger than 0.2mm if the through hole width 136 is 3mm) Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mokler and Lee as applied to claim 18 above, and further in view of Emil F. Blase et al. (US 3670210 A) herein after referred to as Blase. Regarding claim 20 Mokler in view of Lee teaches: The printed circuit board assembly according to claim 18, Mokler further teaches wherein the through hole (fig. 1a and fig 4 element 112) is positioned directly under the plurality of capacitors (108), and wherein the heat sink (120) is in contact with the plurality of capacitors. Mokler does not teach the contact being direct. Instead, the capacitors and heat sink are in contact through the thermal interface material 144 Blase teaches the direct contact between capacitor and heat sink. (See Abstract and Para. [5]) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Mokler and Lee such that the contact between capacitors and the heat sink is direct contact, as described in Blase because the modification allows for a heat transfer path of high thermal conductivity and effective heat management. (See the Abstract and Col. 1 lines 26-46 of Blase) Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Friday, 9:00a.m. - 5:00p.m. ET.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, SUE PURVIS can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAIME LYNN SPRENGER/Examiner, Art Unit 2893 /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Dec 08, 2023
Application Filed
Feb 24, 2026
Non-Final Rejection mailed — §103
May 19, 2026
Response Filed
Jul 16, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12677542
DISPLAY PANEL AND ELECTRONIC APPARATUS INCLUDING THE SAME
2y 7m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 1 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
2y 7m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1 resolved cases by this examiner. Grant probability derived from career allowance rate.

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