Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/19/2024 was filed after the mailing date of the Non-final rejection on 3/6/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The formal drawings filed on 12/8/2023 have been approved by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-14 and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Nakano (WO 2021/225119).
With respect to Claims 1, 4, 5, 11, and 12, the paragraphs used in this rejection using Nakano are from the English version of this reference. Nakano teaches providing a wafer 10, 13 having a front side and a back side and a metal layer having a gate pad 70 and a source pad 75 at the front side. A silicon layer (i.e. SiC) at the back side wherein the silicon layer has a pre-process thickness (i.e. not less than 1 micrometer and less than 1000 micrometers). Molding a structural support coating 80 (i.e. epoxy resin which is a polymer) over the gate pad and source pad at the front side of the wafer 10, 13. Back-side processing (i.e. thinning step) the wafer 10 to remove a portion of the silicon layer so that the silicon layer has a post-process thickness. The post-process thickness is less than the pre-process thickness. Removing (i.e. by grinding) the structural support coating 80 by at the front side of the wafer sufficiently to expose the gate pad 70 and source pad 75 (see paragraphs 47, 51-53, 113, 125, 126, 159-171; Figs. 6F-6H and 7).
With respect to Claim 2, Nakano teaches the pre-process thickness of the silicon layer is greater than or equal to 700 µm (i.e. 600 micrometers which less than 1000 micrometers) (see paragraphs 51 and 52).
With respect to Claim 3, Nakano teaches the post-process thickness of the silicon layer is less than or equal to 50 µm (i.e. 40 micrometers which is less than 100 micrometers (see paragraphs 51 and 52).
With respect to Claims 6, 7, and 14, Nakano teaches plating (i.e. made of Cu)the front side of the wafer 10, 13 to build up the gate pad and source pad (see paragraphs 97, 139, and 143).
With respect to Claims 8 and 16, Nakano teaches adding a drain pad layer on the back side of the wafer (see paragraphs 80 and 81).
With respect to Claims 9, 17, and 18, Nakano teaches plating the front and back sides of the wafer with oxidizing inhibiting layers 90 (i.e. Ni which is anti- oxidizing ) and Au (see paragraphs 81, 270 and 271).
With respect to Claim 10, Nakano teaches singulating the wafer to form individual chips (see paragraphs 163).
With respect to Claim 2, Nakano teaches a surface of the structural support coating, a surface of the source pad, and a surface of the gate pad are coplanar (see Figs. 6H and 7.).
Allowable Subject Matter
6. Claims 19 and 20.
7. Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the
limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowance subject
matter: none of the prior art of record does not teach or suggest the combination of the electronic device has an RDS(on) value less than 10 milliohms in claim 15.
A drain pad layer on the back side of the silicon layer. Oxidizing inhibiting layers on the front side of the metal layer and the back side of the silicon layer, wherein the field effect transistor has an RDS(on) value less than 10 milliohms in claim 19.
The prior art made of record and not relied upon is cited primarily to show the
product of the instant invention.
Conclusion
8. Any inquiry concerning the communication or earlier communications from the
examiner should be directed to Alonzo Chambliss whose telephone number is (571)
272-1927.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number
for the organization where this application or proceeding is assigned is (571) 273-8300.
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AC/March 6, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897
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