DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-10) and Species A (Fig. 5) in the reply filed on 5/4/26 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are: removing a portion of the insulating liner to expose a bottom surface of the sacrificial buried layer. If the bottom surface of the sacrificial buried layer is exposed and the insulating liner is conformally formed on a sidewall of the buried trench in claim 2, then a portion of the insulating liner has to be removed to expose a bottom surface of the sacrificial buried liner in a prior step in claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 9, 10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Application Publication No. 2023/0178433 (Xie ‘433).
Xie ‘433 discloses
1. A method of manufacturing an integrated circuit device, the method comprising:
forming a preliminary channel stack 20 on a substrate 10 comprising a first surface and a second surface opposite to the first surface, the preliminary channel stack 20 comprising a plurality of sacrificial layers 22 and a plurality of channel layers 24;
forming a preliminary channel pattern 20’ and a fin-type active region 14 by removing a portion of the preliminary channel stack 20 and a portion of the substrate 10, wherein a sidewall of the preliminary channel pattern 20’ and a sidewall of the fin-type active region 14 are aligned with each other to define a buried trench 34;
forming a sacrificial buried layer 40 in the buried trench 34;
forming a source/drain region 50 on the fin-type active region 14;
forming a power via 44 on the sacrificial buried layer 40, the power via 40 being electrically connected to the source/drain region 50;
removing a portion of the substrate 10 (Fig. 10) from the second surface of the substrate 10 to expose a bottom surface of the sacrificial buried layer 40;
removing the sacrificial buried layer 40 and forming a backside buried wiring layer 74 in the buried trench 34, the backside buried wiring layer 74 being electrically connected to the power via 44; and
forming a backside wiring structure 80 on the second surface of the substrate 10, the backside wiring structure 80 being electrically connected to the backside buried wiring layer 74.
Xie ‘433 discloses (at least Fig. 5)
9. The method of claim 1, wherein the fin-type active region 14 comprises a plurality of fin-type active regions 14 extending in a first horizontal direction, the plurality of fin-type active regions 14 comprise a first fin-type active region 14 and a second fin-type active region 14 adjacent to each other in a second horizontal direction, and the sacrificial buried layer 40 is arranged between the first fin-type active region 14 and the second fin-type active region 14, in a plan view.
Xie ‘433 discloses (at least Fig. 8)
10. The method of claim 9, wherein the forming of the power via 44 comprises forming the power via 44 between a first source/drain region 50 and a second source/drain region 50, the first source/drain region positioned on one side of the first fin-type active region 14, and the second source/drain region 50 positioned on one side of the second fin-type active region 14.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2, 3, 5-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie ‘433 as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2024/0021708 (Lan).
Xie ‘433 fails to disclose
2. The method of claim 1, further comprising:
conformally forming an insulating liner on a sidewall of the buried trench before the forming of the sacrificial buried layer; and
forming a buried insulating layer in the buried trench and on the sacrificial buried layer after the forming of the sacrificial buried layer.
Lan teaches, to the extent taught and understood,
A method comprising:
conformally forming an insulating liner 202 on a sidewall of the buried trench 206 before the forming of the sacrificial buried layer 210; and
forming a buried insulating layer 214 in the buried trench 206 and on the sacrificial buried layer 210 after the forming of the sacrificial buried layer 210.
It would have been obvious as a person of ordinary skill in the art before the effective filing date of the claimed invention to form an insulating liner and a buried insulating layer in Xie ‘433. The motivation would be to provide a bigger sacrificial layer, electrical isolation as taught by Lan ([0033]-[0042], and to prevent leakage, and alleviate mechanical stress. Further, since the semiconductor substrate 100 has been thinned, the aspect ratio of the trench 244 is within an acceptable range. The filling of the conductive material layer may thus be performed well ([0107], [0120]).
Lan teaches
3. The method of claim 2, wherein a portion of the insulating liner 202 arranged on an inner wall of the buried trench 206 is in contact with a sidewall of the backside buried wiring layer 224A.
Xie ‘433 fails to disclose
5. The method of claim 2, further comprising:
forming a sacrificial gate electrode on the fin-type active region adjacent to the source/drain region after the forming of the sacrificial buried layer; and
forming an inter-gate dielectric to cover the sacrificial gate electrode and the source/drain region.
Lan teaches
A method comprising:
forming a sacrificial gate electrode 120A / 120B on the fin-type active region 106A / 106B adjacent to the source/drain region 138 after the forming of the sacrificial buried layer 210; and
forming an inter-gate dielectric 140 to cover the sacrificial gate electrode 120A / 120B and the source/drain region 138.
It would have been obvious as a person of ordinary skill in the art before the effective filing date of the claimed invention to form a sacrificial gate electrode and an inter-gate dielectric in Xie ‘433. The motivation would be they are well-known in the method of making an integrated circuit as shown in Lan. See MPEP 2144.03.
Lan teaches
6. The method of claim 5, wherein the forming of the power via 224A / 224B comprises:
forming a power via hole 220A / 220B to expose an upper surface of the sacrificial buried layer 210 by removing a portion of the inter-gate dielectric 140 and a portion of the buried insulating layer 214;
forming the power via 224A / 224B in the power via hole 220A / 220B, the power via 224A / 224B being in contact with the upper surface of the sacrificial buried layer 210;
forming a first contact hole (Fig. 2L) to expose an upper surface of the source/drain region 138 by removing a portion of the inter-gate dielectric 140; and
forming a first contact in the first contact hole, the first contact being in contact with an upper surface of the power via 224A / 224B and the upper surface of the source/drain region 138 (Fig. 2M).
It would have been obvious as a person of ordinary skill in the art before the effective filing date of the claimed invention to form a power via with an inter-gate dielectric in Xie ‘433. The motivation would be an inter-gate dielectric is well-known in the method of forming an integrated circuit as discussed in Lan. See MPEP 2144.03.
Xie ‘433 discloses
7. The method of claim 5, wherein the forming of the preliminary channel pattern 20’ and the fin-type active region 14 to define the buried trench 34 comprises:
forming the preliminary channel pattern 20’and the fin-type active region 14 to define a device isolation trench 30’ having a first depth, by removing a portion of the preliminary channel stack 20 and a portion of the substrate 10; and
forming the buried trench 34 having a second depth, by removing a portion of the substrate 10 exposed at a bottom of the device isolation trench 30’.
Lan teaches ([0034])
8. The method of claim 1, wherein the sacrificial buried layer 210 comprises silicon nitride or silicon oxynitride.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie ‘433 in view of Lan as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2023/0086033 (Xie ‘033).
The combination of references fails to teach
4. The method of claim 2, wherein the buried trench has an inclined sidewall, and a first width of the buried trench at a level of the first surface of the substrate, is greater than a second width of the buried trench at a bottom surface of the buried trench.
Xie ‘033 teaches
A method comprising:
wherein the buried trench (Fig. 1B) has an inclined sidewall, and a first width of the buried trench at a level of the first surface of the substrate 102, is greater than a second width of the buried trench at a bottom surface of the buried trench.
It would have been obvious as a person of ordinary skill in the art before the effective filing date of the claimed invention to form the buried trench with an inclined sidewall in the modified method of Xie ‘433. The motivation for an inclined shape would be a matter of routine engineering considerations. See MPEP 2144.05. Further, such a shape would prevent voids during gap-fill processes, relieve mechanical stress, and improve the step coverage of the BPR deposited inside the trench.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. WO Publication No. 2023-052326 (Xie ‘326), U.S. Patent Application Publication Nos. 2021/0351303 (Ju), 2023/0268389 (Jain) teach a method of manufacturing an integrated circuit device including a power via, a sacrificial buried layer, and a backside wiring structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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