Prosecution Insights
Last updated: October 02, 2026
Application No. 18/533,285

DISPLAY ELEMENT AND MANUFACTURING METHOD THEREOF

Non-Final OA §102
Filed
Dec 08, 2023
Priority
Jun 27, 2023 — TW 112123854
Examiner
ERDEM, FAZLI
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
AUO Corporation
OA Round
3 (Non-Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
925 granted / 1083 resolved
+17.4% vs TC avg
Strong +16% interview lift
Without
With
+15.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
21 currently pending
Career history
1102
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
50.2%
+10.2% vs TC avg
§102
38.0%
-2.0% vs TC avg
§112
7.4%
-32.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1083 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/21/2026 has been entered. Allowable Subject Matter Claims 1-13 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding Claim 1, prior art failed to disclose or fairly suggest a display element comprising, along with other recited claim limitations, wherein the first spacer and the second spacer are discrete structures separated from each other by a distance, with a portion of the first transparent molding layer being disposed between the first spacer and the second spacer; anda transparent conductive layer, located on the top surface of the first transparent molding layer and the top surface of the second semiconductor layer, and extending from the second semiconductor layer to the second electrode by spanning the distance between the first spacer and the second spacer, as discussed during the interview held on 7/21/2026, as amended on 8/19/2026 and as argued on pages 9-14 of the remarks filed on 8/19/2026. Claims 2-13 depend from claim 1 hence are allowed for the same reason therein. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (20200343425). Regarding Claim 20, in Figs. 2A-2C and 5A-5C, Tsai et al. discloses a display element, comprising: a first spacer 302a; a second spacer 302a, located on one side of the first spacer; at least one first electrode 210, surrounded by the first spacer; a second electrode 208, surrounded by the second spacer; at least one light-emitting diode (LED) structure, located on the first electrode, and comprising: a first semiconductor layer, located on the first electrode; a multi-quantum well layer, located on the first semiconductor layer; and a second semiconductor layer 202/204/206, located on the multi-quantum well layer; a reflective layer 302b, located on a sidewall of the first spacer facing the LED structure; a first transparent molding layer 300, located on the reflective layer and surrounding the LED structure, wherein a top surface of the second semiconductor layer is higher than a top surface of the first transparent molding layer; and a transparent conductive layer, located on the top surface of the first transparent molding layer and the top surface of the second semiconductor layer, and extending from the second semiconductor layer of the LED structure to the second electrode, wherein the second electrode 208 is disposed laterally away from the LED structure. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAZLI ERDEM/Primary Examiner, Art Unit 2812 9/12/2026
Read full office action

Prosecution Timeline

Dec 08, 2023
Application Filed
Mar 26, 2026
Non-Final Rejection mailed — §102
May 29, 2026
Response Filed
Jun 12, 2026
Final Rejection mailed — §102
Jul 21, 2026
Examiner Interview Summary
Aug 19, 2026
Request for Continued Examination
Aug 21, 2026
Response after Non-Final Action
Sep 15, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12745568
MAGNETIC MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
2y 10m to grant Granted Sep 22, 2026
Patent 12740173
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURED USING THE SAME
2y 7m to grant Granted Sep 15, 2026
Patent 12740395
INTEGRATED CIRCUIT DEVICES INCLUDING A CONDUCTIVE VIA AND METHODS OF FORMING THE SAME
3y 0m to grant Granted Sep 15, 2026
Patent 12733201
METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR HAVING ENHANCED HIGH-FREQUENCY PERFORMANCE AND METHODS FOR FABRICATING SAME
4y 0m to grant Granted Sep 08, 2026
Patent 12733192
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
3y 6m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+15.9%)
2y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1083 resolved cases by this examiner. Grant probability derived from career allowance rate.

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