DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention Group I, claims 1-13 in the reply filed on 3/5/2026 is acknowledged.
Claims 14-19 (invention Group II) are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected (invention Group II, method) there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/5/2026
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sakariya et al. (2014/0159064).
Regarding Claim 1, in Figs. 5A and 15G, Sakariya et al. discloses a display element, comprising: a first spacer 110 (the right one); a second spacer 110 (the left one), located on one (left) side of the first spacer; at least one first electrode 420, surrounded by the first spacer 110; a second electrode 470, surrounded by the second spacer; at least one light-emitting diode (LED) structure450 (p-n diode), located on the first electrode 470, and comprising: a first semiconductor layer 414 (top or bottom one), located on the first electrode 420; a multi-quantum well layer 416 , located on the first semiconductor layer; and a second semiconductor layer 414, located on the multi-quantum well layer; a reflective layer 132, located on a sidewall of the first spacer 110 (right one) facing the LED structure; a first transparent molding layer 142/150 (see paragraph 0125 and 0149), located on the reflective layer 132 and surrounding the LED structure, wherein a top surface of the second semiconductor layer 414 (the other of the top or bottom one) is higher than a top surface of the first transparent molding layer 142/150 (see paragraph 0109 and 0139); and a transparent conductive layer 160 (see paragraph 0150 and 0151), located on the top surface of the transparent molding layer 142/150 and the top surface of the second semiconductor layer 414, and extending to the second electrode 470.
Regarding Claim 2, the sidewall of the first spacer 110 (the right one) is a stepped surface (tapered).
Regarding Claim 3, included angle between the sidewall of the first spacer 110 (the right one) and a lower surface is 30-55 degrees (see paragraph 0117).
Regarding Claim 4, a light-absorbing structure 170, located on the transparent conductive layer 160 and surrounding a top portion of the second semiconductor layer 414 (the other of the top or bottom one)
Regarding Claim 5, a second transparent molding layer 142/150, located on the transparent conductive layer 160 and surrounded by the light-absorbing structure 170.
Regarding Claim 6, a substrate 100, located on the second transparent molding layer 142/150 (see paragraph 0111, 0113, 0116, 0117).
Regarding Claim 7, the substrate 100 has a light-absorbing layer inside, and the light-absorbing layer is located on the light-absorbing structure (see paragraph 0111, 0113, 0116, 0117).
Regarding Claim 8, the substrate 100 has a light-reflective layer inside, and the light-reflective layer is located on a sidewall of the light-absorbing layer (see paragraphs 0111 and 0113)
Regarding Claim 9, the substrate 100 has a light-reflective layer inside, and the light-absorbing layer is located on the light-absorbing structure (see paragraphs 0111 and 0113)
Regarding Claim 10, the substrate 100 has a thickness of less than 0.5 mm (see paragraph 0116, 0117 and 0139).
Regarding Claim 11, the reflective layer 132, the first electrode 420 and the second electrode 470 are formed by a same film layer (see paragraph 0143)
Regarding Claim 12, there are three LED structures arranged in a column, the three LED structures are a red LED structure, a green LED structure and a blue LED structure respectively, there are three first electrodes, the first semiconductor layers of the three LED structures are electrically connected to the three first electrodes respectively, and the second semiconductor layers of the three LED structures are electrically connected to the second electrode (see Figs. 5A, 5B and paragraphs 0008, 0126, 0139, 0141)
Regarding Claim 13, there are a plurality of LED structures arranged in a plurality of columns, and the LED structures in each of the columns comprise a red LED structure, a greenLED structure and a blue LED structure, there are a plurality of first electrodes, the first semiconductor layers of the LED structures are electrically connected to the first electrodes respectively, and the second semiconductor layers of the LED structures are electrically connected to the second electrode (see Figs. 5A, 5B and paragraphs 0008, 0126, 0139, 0141)
Cited Prior Art NOT Relied Upon
Examiner is including Pinos 20230125929 and Pinos 20230207753 as pertinent prior art references that are NOT relied upon on this rejection but that do disclose patterned/roughened surface for the spacer/reflective layer in order to convert laterally extending photo/light to upward/vertical photo/light in order to increase the emission efficiency.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FAZLI ERDEM/Primary Examiner, Art Unit 2812
3/18/2026