Prosecution Insights
Last updated: July 17, 2026
Application No. 18/533,315

INTEGRATED DEVICE, SEMICONDUCTOR DEVICE, AND INTEGRATED DEVICE MANUFACTURING METHOD

Non-Final OA §102§103§112
Filed
Dec 08, 2023
Priority
Jun 11, 2021 — continuation of PCTCN2021099575
Examiner
YUSHINA, GALINA G
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Huawei Technologies Co., Ltd.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
861 granted / 1085 resolved
+11.4% vs TC avg
Strong +17% interview lift
Without
With
+16.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
36 currently pending
Career history
1115
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
72.3%
+32.3% vs TC avg
§102
5.8%
-34.2% vs TC avg
§112
19.5%
-20.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1085 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Acknowledged Applicant’s election, with traverse, Species 2 of Invention Group I (directed to an integrated device) shown in Figs. 5-6 and Claims 1-8 in the response to Restriction Requirements filed 04/27/26 is acknowledged. Traversal was based on the Applicant’ assumption that all claims are linked together by a single concept, contrary to the MPEP-based statement of the Restriction Requirements that a linking subject matter between different inventions as a specific technical feature takes place only when a specific technical feature is new in the art; but the last is not fulfilled for the current application, since Claim 1, as interpreted, is rejected by the current Office Action, using the same prior art that was referenced by the Restriction Requirements. At the same time, as it is common in examination of a PCT application in a national stage, if the examined claims are allowed, claims that were initially withdrawn from consideration for examination and containing all limitations of the examined independent allowable claim would be considered, on later stages of examination, for rejoinder. Responding to Restriction Requirements, Applicant stated that the Restriction Requirements contained a typographical error in referring to Claims 1-18, while, per Applicant, the set of claims does not have Claim 13 and contained only Claims 1-12 and 14-19. In response to the statement, Examiner points out that, currently, the only one set of claims in the application does have Claim 13 and contains Claims 1-18. Status of Claims Claims 9-18 are withdrawn from further consideration as being drawn to nonelected inventions. Claims 1-8 are examined on merits herein. Specification The disclosure is objected to because of the following informalities: Paragraph 0021 of the published application US 2024/0113103 states that the first dielectric layer includes a P-type gallium nitride; please, be reminded that a gallium nitride (as well as an aluminum gallium nitride) is a semiconductor. The disclosure of the current application shows no evidence of knowledge that a metal nitride (such as a titanium nitride, a first time referenced by paragraph 0073 of the published application) used as layer 25 (Figs. 2 and 5) and identified as “a first metal layer” by multiple paragraphs, Abstract, and claims of the application) - is not a metal, but a metal nitride. Specification is unclear with respect to a term: “a gate”. This word is commonly used either referencing to a transistor or to a gated a capacitor, but no references to a transistor or to a gated capacitor is made in the specification, and use of the term “gate” is unclear. Paragraph 0087 of the published application refers to a metal layer 210 when describing Figs. 2-4, while layer 210 is shown in Fig. 5, not in Figs. 2-4. Since the detailed description of the application does not make a reference to Figs. 5 and 6, Examiner suggests incorporating a reference to Figs. 5-6 in the detailed description of the specification. In addition, Examiner suggests either making references to dash lines in Fig. 6 as being (or at least, related to) first and second conductor structures, or to show the first and second conductor structures in Figs. 5 and/or 2 (the last suggestion is based on an MPEP requirement to show the claimed subject matter in the figures of the application). Paragraph 0088 of the published application refers to a “gate metal” as to layer 57, while in other paragraphs, a gate metal is identified by number 27. Paragraph 0088 is not clear in identifying layers creating a junction capacitor – it teaches that a junction capacitor is created by layers 25, 24, and 211, but does not mention a semiconductor layer 23 disposed between layers 24 and 211. Appropriate corrections/clarifications are required. Claim Objections Claims 1, 2, 3 and 6 are objected to because of the following informalities: Claims 1-3 recite: “gate metal”, which is unclear, since the application does not clearly teach/describes any transistor or a gated capacitor. Unless the Applicant is willing to clarify for which component “a gate metal” is used, the Examiner suggests replacing words: “gate metal layer” with: “second electrically-conductive layer” or “second metal layer”. Claim 3 recites: “a two-dimensional electron gas is comprised below the aluminum gallium nitride layer”. For a better clarity, the Examiner suggests changing the recitation to: “a two-dimensional electron gas is contained below the aluminum gallium nitride layer”. Claim 6 recites: “comprise P-type gallium nitride or P-type aluminum gallium nitride”. Examiner suggests adding articles to the recitation, e.g.: “comprise a P-type gallium nitride or a P-type aluminum gallium nitride”. Appropriate corrections are required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-8 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. In re Claims 1 and 7: Claim 1 recites: “first metal layer”, while Claim 7, dependent on Claim 1, recites: “the first metal layer comprises titanium nitride or tungsten”. The combination of recitation is unclear, since titanium nitride is a nitride of a metal and not a metal. Appropriate correction is required to clarify the claim language. For this Office Action, the cited recitations of “first metal layer” in Claims 1, 7, and all other relevant claims (including Claims 2, 3) were interpreted as: “first electrically-conductive layer” In re Claims 1-3: Claims 1-3 use words: “gate metal layer”, but the current application does not clearly identify any component having a gate as its element, in view of which, the current Office Action uses recitations: “gate metal layer” as “metal layer”. In re Claim 2: Claim 2 recites: “the gate metal layer and the first metal have opposite polarities, and the second metal layer and the gate metal layer have opposite polarities”. The recitation is unclear, since opposite polarities may have semiconductors having dopants of opposing polarities (one being an n-type and another being a p-type). Regarding other electrically conductive materials, including metals, a reference to different polarities may be made only in connection to applied potentials or to applied voltages, e.g., during operation of a capacitor when voltages or potentials with opposite polarities are applied to two electrodes of the capacitor. Appropriate correction is required to clarify the claim language. For this Office Action, the cited limitations were interpreted as: “during operation of the integrated device, the gate metal layer is connected to a voltage of a first polarity and the first electrically-conductive layer and the second metal layer are connected to a voltage of a second polarity, the first polarity being opposite to the second polarity” In re Claim 4: Claim 4 has a same issue with “polarities” as Claim 2, which shall be appropriately corrected. For this Office Action, Claim 4 was interpreted in a manner similar to that shown for Claim 2. In re Claim 6: Claim 6 recites: “The integrated device according to Claim 1, wherein the P-type conductive layer comprises”. There is a lack of antecedent basis for using “P-type conductive layer” with article “the”, since Claim 1 does not recite: “a P-type conductive layer” – Claim 3 does. Appropriate correction is required to clarify the claim language. For this Office Action, Claim 6 was interpreted as: “The integrated device according to Claim 3, wherein the P-type conductive layer comprises”. In re Claim 8: Claim 8 is rejected under 35 U.S.C. 112(b) due to dependency on Claim 1. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. As far as the claims are understood, Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 10,026,731). In re Claim 1, Yang teaches an integrated device (of Fig. 4, column 10 lines 25-34), including a capacitor 430 and a transistor 410, the capacitor comprising: a first metal layer CC (column 11 line 45); a first dielectric layer 432 (column 11 line 7) disposed on the first metal layer CC; a second dielectric layer 434 (column 11 line 4) disposed on the first dielectric layer 432; a gate metal layer M1 (column 11 line 3) disposed between the first dielectric layer 432 and the second dielectric layer 434; and a second metal layer M2 (column 11 line 4) disposed on the second dielectric layer 434, wherein the first metal layer CC, the first dielectric layer 432, and the gate metal layer M1 form a first capacitor C2 (column 11 lines 10-13); the second metal layer M2, the second dielectric layer 434, and the gate metal layer M1 form a second capacitor C1 (column 11 lines 2-6); and the first metal layer CC is connected to the second metal layer M2 by a first conductor structure V1/M1/V2- (column 11, lines 29 and 46, as related to V1 and V2), so that the first capacitor C2 and the second capacitor C1 are connected in parallel (column 11 lines 1-2). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. As far as the claims are understood, Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Yang. In re Claim 2, Yang teaches the integrated device of Claim 1 as cited above, wherein the gate metal layer and the gate metal layer create two electrodes of the first capacitor and the gate metal layer and the second metal layer create two electrodes of the second capacitor. Although Yang does not state anywhere that the gate metal layer and the first metal layer have opposite polarities, and the second metal layer and the gate metal layer have opposite polarities, e.g., in accordance with the claim interpretation, “during operation of the integrated device, the gate metal layer is connected to a voltage of a first polarity and the first electrically-conductive layer and the second metal layer are connected to a voltage of a second polarity, the first polarity being opposite to the second polarity” – it is well-known in the art that for operation of a capacitor in an electrical circuit – voltages of opposite polarities shall be applied to two electrodes of the capacitor: see attached pages from Johnson (NPL) on operation of a capacitor (please, note that Johnson was referenced only as a reminder of basic principles of capacitor operation). Accordingly, it would have been obvious for one of ordinary skill in the art before the effective date of filing the application to apply voltages of different polarities on two electrodes of each of the first and second capacitors. In re Claim 7, Yang teaches the integrated device according to Claim 1 as cited above, including the first metal layer CC. Yang does not explicitly teach that the first metal layer CC comprises titanium nitride or tungsten – he explicitly teaches Ti, Pt. Au, Co or similar materials (column 11 lines 31-33). However, Yang teaches that other metal layers – such as M1 or M2 can be made from tungsten (column 11, lines 48-49). It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Yang device by creating the first metal layer from the same material from which M1 and M2 are created – such as tungsten – when it is desirable to limit a number of metal materials used in creation of the device. In addition, in accordance with MPEP 2144.07 Art Recognized Suitability for an Intended Purpose, “The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination” in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) or Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988). Allowable Subject Matter As far as the claims are interpreted, Claim 3 contains allowable subject matter (while Claims 4-6 and 8 depend on Claim 3). Reason for Identification of Allowable Subject Matter The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitations of Claim 3 as: “a P-type conductive layer disposed below the first metal layer; and an aluminum gallium nitride layer disposed below the P-type conductive layer, wherein a two-dimensional electron gas is comprised below the aluminum gallium nitride layer; the first metal layer, the P-type conductive layer, and the two-dimensional electron gas form a third capacitor”, in combination with other limitations of Claim 3 and with all limitations of Claim 1, on which Claim 3 depends: Although Yang’ transistor could be a HEMT, inherently comprised a two-dimensional electron gas, and although Yang teaches an embodiment (Figs. 8) in which a capacitor is created as three capacitors connected in parallel, the third transistor in the Yang structure of Figs. 8 is not created from any semiconductor layer or from an inherently existing a 2D electron gas of the integrated device HEMT. Other prior arts of record, including Takeuchi et al. (US 2009/0218578), Jones et al. (US 2021/0217883), or Kurokawa et al. (US 2013/0026541), teaching an integrated device comprised an aluminum gallium nitride layer (in Takeuchi) and/or a two-dimensional electron gas, where Takeuchi and Jones teach that one electrode of a capacitor can be created from a two-dimensional electron gas, - cannot be used for Claim 3 on their own, since they do not teach a capacitor comprised three parallel connected capacitors, and these prior arts cannot be used for modification of the Yang integrated device, since there is no combination of these arts that provides a motivation for substitution a metal layer of Yang that is used for creating an electrode of the third capacitor with a 2D electron gas of Takeuchi, Jones, or Kurokawa. Conclusion Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible). Examiner interviews are available. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300; a fax phone number of Galina Yushina is 571-270-8440. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center - for more information about Patent Center and visit https://www.uspto.gov/patents/docx - for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800, United States Patent and Trademark Office E-mail: galina.yushina@USPTO.gov Phone: 571-270-7440 Date: 05/27/26
Read full office action

Prosecution Timeline

Dec 08, 2023
Application Filed
Jun 03, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685230
SEMICONDUCTOR DEVICE
2y 10m to grant Granted Jul 14, 2026
Patent 12677439
SEMICONDUCTOR DEVICES WITH SELECTIVELY DOPED GATE ELECTRODE STRUCTURE
3y 2m to grant Granted Jul 07, 2026
Patent 12666653
METAL OXIDE THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY DEVICE
3y 3m to grant Granted Jun 23, 2026
Patent 12666954
SEMICONDUCTOR DEVICE INCLUDING VARIABLE RESISTANCE PATTERN AND ELECTRONIC SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE
3y 1m to grant Granted Jun 23, 2026
Patent 12660190
INTERVENING POLYSILICON MATERIALS THAT ARE THICKER AT DISTAL EDGES THAN AT PILLARS DEFINING MEMORY CELLS AND RELATED APPARATUSES, SYSTEMS, AND METHODS
3y 9m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
96%
With Interview (+16.8%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1085 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month