Prosecution Insights
Last updated: October 02, 2026
Application No. 18/533,354

TRENCH GATE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Final Rejection §112
Filed
Dec 08, 2023
Priority
Jan 19, 2023 — JP 2023-006764
Examiner
BOOTH, RICHARD A
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
MIRISE Technologies Corporation
OA Round
2 (Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
921 granted / 1072 resolved
+17.9% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
23 currently pending
Career history
1096
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
58.8%
+18.8% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
7.5%
-32.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1072 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-4 and 6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The specification, as originally filed, does not provide support for the surface of the upper electrode being in contact with the semiconductor substrate. It appears that the upper electrode is in contact with the gate insulating film 24. Clarification is required. Response to Arguments Applicant’s arguments with respect to claim(s) 1-4 and 6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RICHARD A BOOTH/ Primary Examiner, Art Unit 2812 August 17, 2026
Read full office action

Prosecution Timeline

Dec 08, 2023
Application Filed
Apr 07, 2026
Non-Final Rejection mailed — §112
Jul 06, 2026
Applicant Interview (Telephonic)
Jul 06, 2026
Response Filed
Jul 06, 2026
Examiner Interview Summary
Aug 20, 2026
Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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FLASH MEMORY WITH STACKABLE MEMORY CELLS
3y 4m to grant Granted Sep 29, 2026
Patent 12751076
INTEGRATION OF A VERTICAL DIODE AND A TRANSISTOR
2y 9m to grant Granted Sep 29, 2026
Patent 12751152
DISPLAY APPARATUS, DISPLAY MODULE, ELECTRONIC DEVICE, AND METHOD FOR FABRICATING DISPLAY APPARATUS
2y 9m to grant Granted Sep 29, 2026
Patent 12741864
INERTIAL MEASUREMENT UNIT
3y 11m to grant Granted Sep 22, 2026
Patent 12745455
SEMICONDUCTOR FABRICATION PROCESS
3y 4m to grant Granted Sep 22, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+8.3%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1072 resolved cases by this examiner. Grant probability derived from career allowance rate.

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