Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of group I in the reply filed on 03/06/26 is acknowledged. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim (s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naito WO 2018/030440 in view of Masanori et al., JP 2018-125490 . Naito shows the invention substantially as claimed including a trench gate semiconductor device, comprising: A semiconductor substrate (for example, 10) ; A first trench (30,40) provided in an upper surface of the semiconductor substrate; A second trench (30,40) provided in the upper surface of the semiconductor substrate and spaced apart from the first trench in a lateral direction; A gate insulating film (32,42) covering an inner surface of each of the first trench and the second trench; A gate electrode 34 disposed in each of the first trench and the second trench and insulated from the semiconductor substrate by the gate insulating film; and An upper electrode 52 covering the upper surface of the semiconductor substrate, wherein the semiconductor substrate includes: An n-type first semiconductor region 12 that is disposed between the first trench and the second trench and in contact with the upper electrode; A p-type body region 14 that is disposed between the first trench and the second trench below the first semiconductor region , and extends from a position in contact with the gate insulating film in the first trench to a position in contact with the gate insulating film in the second trench, and An n-type second semiconductor region (for example, 16) that is disposed between the first trench and the second trench below the body region, extends from a position in contact , wherein there is a maximum value of a distance between the first trench and the second trench in the lateral direction in a depth range in which the body region is disposed, and the distance between the first trench and the second trench at the upper surface of the semiconductor substrate is larger than the maximum value (see particularly fig. 35 of the WO , and additionally see “Description of Preferred Embodiments at page 4 of translation to page 8 of translation, for example, and page 21 of translation) . Naito does not expressly disclose where the maximum value of the distance is less than 200 nanometers. Masanori et al. discloses where trenches are separated by a distance of at least 100 nanometers in order to prevent adjacent doped junctions from contacting each other (see translation of paragraph 0037). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Naito so as to have trench regions separated by at least 100 nanometers as required by Masanori et al. because in such a way adjacent trench regions will be adequately isolated. With regard to the claimed distance or spacing being less than 200 nanometers, note that the spacing being at least 100 nanometers represents an overlapping range that establishes a prima facie case of obviousness (see MPEP 2144.05). For instance, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Naito so as to include the trench spacing of Masanori et al. in order to provide adequate isolation between device regions. Concerning dependent claim 2, note that Naito expressly discloses a trench gate semiconductor device, wherein the distance between the first trench and the second trench decreases from the upper surface of the semiconductor substrate toward a lower side (see, for example, fig. 35 of Naito) . With respect to dependent claim 3, Naito discloses a trench gate semiconductor device wherein a width of each of the first trench and the second trench in the lateral direction increases towards a bottom end (see, for example, fig. 35 of Naito) . As to dependent claim 4, note that Naito discloses a side surface of each of the first trench and the second trench has a first surface portion connecting to the upper surface of the semiconductor substrate and a second surface portion extending from a lower end of the first surface portion, at least a part of the first surface portion is a curved surface, and an angle defined with respect to a vertical line defined between the first surface portion and upper surface of the semiconductor substrate at the trench/substrate interface is smaller than an angle defined between the second curved lower portion and the upper surface of the semiconductor substrate also using a vertical line as the reference point (see fig. 46, for example) . Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent 8,089,122 discloses a tapered gate trench (see, for example, fig. 2A, for example). Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT RICHARD A BOOTH whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-1668 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday to Friday, 8:30 to 5:00 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Christine Kim can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-8458 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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