Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 3/8/2024, 4/18/2024, 8/6/2024, 1/8/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-6, 11, 13-15, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Treu (US 20090068803 A1).
Regarding claim 1, Treu discloses, in FIG. 2A, a semiconductor structure. Paragraph 0019 states “[a]lthough not illustrated in FIG. 1A, a drain contact would be provided on the bottom of the substrate when . . . completed” (drain cathode electrode and substrate), the examiner notes that although this does not directly refer to FIG. 2A, it is inherent that the VJFET of FIG. 2A (see paragraph 007) has a drain-cathode electrode below the substrate, by the definition of a VJFET (that is, that the source and drain must be opposite one another vertically). FIG. 2A further discloses body region 2 over the substrate comprising a top surface, and a source area 4 (first source region) extending into the body region from the top surface. FIG. 3A clarifies that the gate metallization 12a of FIG. 2A is in a U-shaped region (first gate trench, note the n+ region having two peaks, with the p+ doped trench therebetween). In addition, FIG, 2A discloses P doped region 14, which is in a U-shaped trench of its own, below the source region (anode region/anode trench). Paragraph 0025 discloses that the P+ doped portions of the anode “are short-circuited with the source-areas 4, thus forming the built-in PN-diode.” This discloses that the electrode 6 is continually formed onto the second source region (forming the anode trench). FIG. 2A discloses a source-metallization 6 (first source electrode), and a first gate electrode (unlabeled, labeled 12a in FIG 1A) over a portion of the first gate trench and between the first gate trench and the anode trench to the right thereof (see FIG. 3A); source electrode 6 extends into the anode trench, further defining the anode electrode, and electrically coupling the source and anode electrodes. The first gate region forms part of a first VJFET (see paragraph 0016) and the anode region forms part of a vertical diode cell (see paragraph 0025) that is coupled anti-parallel with the first vertical JFET cell (the p-doped anode to the anode electrode, and the n doped region 4 to the source electrode 12, in FIG. 2A, are anti-parallel).
Regarding claim 3, Treu further discloses, in FIG. 2A, that the first gate region and the anode region are doped with a p-type dopant and that a remaining portion of the body region and substrate are doped with an n-type dopant.
Regarding claim 4, Treu further discloses, in FIG. 2A, that the first source electrode and the anode electrode integrally form part of a continuous electrode structure 6, that covers a portion of the first source region, a portion of the first sidewall of the anode trench, and a portion of the bottom of the anode trench.
Regarding claim 5, as explained above, Treu discloses that the first source electrode and the anode electrode integrally form part of a continuous electrode structure that covers at least a portion of the first source region of the first source region, a first side wall of the anode trench, and the bottom of the anode trench.
Regarding claim 6, Treu further discloses, in FIG. 2A, a channel region 10 (first channel region) which is below the first source region and between the first gate region and the anode region.
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Regarding claim 11, FIG 3A discloses a second source region on the other side of the vertical diode cell in a plan view. The examiner notes that the second source region will exist on the top surface of the body region and will have all of the same elements below it as the first source region, as shown by FIG. 2A. This includes second u-shaped gate region having a portion below the second source region defining a second gate trench, a second portion of the anode region below the second source region such that the anode trench is between the first gate trench and the second gate trench, a second source electrode over the second source region and between the second gate trench and the anode trench, a second gate electrode over a portion of a bottom surface of the second gate trench, in which the first electrode, second source electrode, and the anode electrode are electrically coupled, and where the second gate region forms part of a second vertical JFET cell located on the opposite side of the first vertical JFET cell from the vertical diode cell. The examiner notes that the Schottky diode between the first and second JFET cells are anti-parallel (as the current travels from the source to the anode, either right to left or left to right for the first or second JFET cell, respectively).
Regarding claim 13, Treu further discloses, in FIG. 2A, that the first gate region (and therefore the second gate region), and the anode region are doped with a p-type dopant, and that the body and substrate regions are doped with an n-type dopant (note the “n” and “p” labeling).
Regarding claim 14, Treu further discloses in FIG 2A and 3A that the first source electrode and the anode integrally form part of a continuous electrode structure. Additionally, paragraph 0025 states that the P+ doped portions of the anode “are short-circuited with the source-areas 4, thus forming the built-in PN-diode.” This discloses that the electrode structure 6 integrally covers a portion of the first source region, the second source region, the first side wall of the anode trench, the bottom of the anode trench, and a second sidewall of the anode trench.
Regarding claim 15, as explained above, Treu further discloses that the first and second source electrodes and the anode electrodes form part of a continuous electrode structure 6 which covers the first source region, the second source region, a first sidewall of the anode trench, a bottom of the anode trench, and a second sidewall of the anode trench.
Regarding claim 20, Treu further discloses, in FIG. 2A, a channel region below the first source region and between the first gate and anode regions. As explained above, Treu further discloses a second source region. This source region is identical to the first, and thus possesses a channel region below the second source region between the second gate region and the anode region.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 12, and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Treu (US 20090068803 A1).
Regarding claim 2, as explained above, Treu discloses the limitations of claim 1, Treu further teaches, in paragraph 2 “[w]hen high voltages or currents are to be switched, SiC (silicon carbide) is often used as JFET substrate, as this material has superior properties allowing it to withstand high electric fields without electrical breakdown.” It would have been obvious to one having ordinary skill in the art to modify the semiconductor device taught by Treu such that the substrate and body comprise silicon carbide, for the reasons taught by Treu above.
Regarding claim 12, Treu discloses the limitations of claim 11, as explained above. Also as explained above, Treu teaches and motivates the inclusion of silicon carbide in the body and substrate regions.
It would have been obvious to one having ordinary skill in the art to utilize silicon carbide in the body and substrate regions for the regions explained above.
Regarding claim 27, Treu teaches, in Paragraph 0019 states “[a]lthough not illustrated in FIG. 1A, a drain contact would be provided on the bottom of the substrate when . . . completed” (this implies the providing of a substrate and a drain-cathode electrode). Paragraph 0050 states (referring to the manufacturing method depicted in FIGs. 7A – 7C) “ highly doped n.sup.+-layer 48 is already applied on top of an epitactically grown n.sup.--layer 49” (proving a body region). FIG. 7B shows a step of creating a first source region (n+ area 48, see FIG. 3C in which a source electrode is provided, also see FIGs. 1A and 2A). The first source region extends into the body region from a top surface of the body region. A U-shaped gate region is formed, as well as a u-shaped anode trench (see FIGs. 1A and 2A in which one of these trenches is a gate trench, and FIG. 2A in which one of these trenches is an anode trench). FIG. 7C provides the step of forming a source electrode over the first source region and between the first gate trench and anode trench. This electrode is also an anode electrode, over a portion of a bottom of the anode trench, and is electrically coupled to the first source electrode such that the first gate region forms part of a first VJFET cell, and the anode region forms part of a vertical diode cell, which is coupled anti-parallel with the first VJFET cell (see above). Additionally, paragraph 0053 teaches “although not illustrated, all further necessary production processes will be performed . . . for example . . . providing gate contacts.”
It would have been obvious to combine the teachings of Treu to arrive at a method of a method of fabricating a semiconductor device based on the limitations of claim 27. One having ordinary skill in the art is motivated to do so, for example, because this manufacturing process is “. . . a fault-tolerant or alignment-tolerant production process. The device performance is not harmed, even if misalignments in consecutive semiconductor processing steps occur” (Treu, abstract).
Claim(s) 7-8, 9-10, and 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Treu (US 20090068803 A1) in view of Shimizu (US 20100163935 A1).
Regarding claim 7, as explained above, Treu teaches the limitations of claim 6. Treu does not teach a secondary channel region doped with an n-type dopant.
Shimizu teaches, in FIG. 4, a semiconductor structure with a first channel region (labeled EPI, extending into a channel region above) and a second channel region (labeled NR) comprising an n-type dopant, below the first “source region” SR and extending vertically into the first channel region.
It would have been obvious to one having ordinary skill in the art to modify the semiconductor structure taught by Treu such that a second channel region comprising an n-type dopant extends vertically into the first channel region, as taught by Shimizu. One having ordinary skill in the art is motivated to do so in order to, for example, implement a particular doping across the p-n junction in the channel to improve blocking voltage and decrease ON resistance, as taught by Shimizu (see end of paragraph 0074).
Regarding claim 7, Shimizu further teaches the preferred doping profile along the line A-A’ of FIG. 4 in FIG. 5. FIG. 5 shows an n-type doping concentration level which stays consistent from A-A’ (the second channel regio being to the left of the p-n junction), and a p-type doping profile in the first channel region (to the right of the p-n junction) which is near zero at a minimum. Although it is not explicitly stated, one of ordinary skill in the art appreciates that FIG. 5 teaches a maximum concentration of the secondary channel region that is at least 50% higher than a minimum doping concentration (near zero) of the first channel region.
It would have been obvious to one having ordinary skill in the art to further modify the semiconductor device taught by Treu and Shimizu such that a maximum doping concentration of the secondary channel region is at least 50% higher than a minimum doping concentration of the first channel region, as taught by Shimizu. One having ordinary skill in the art is motivated to do so in order to, for example, improve blocking voltage and decrease ON resistance, as taught by Shimizu (see end of paragraph 0074).
Regarding claim 9, as explained above, Treu teaches the limitations of claim 6. However, Treu does not teach secondary channel regions doped with n-typed dopants.
Shimizu teaches, in FIG. 4, a pair of secondary channel regions doped with n-type dopants (see above) extending on vertical inner walls within the first channel region.
It would have been obvious to one having ordinary skill in the art to modify the semiconductor structure taught by Treu such that the channel region comprises a pair of secondary channel regions that are n-type doped and extends on the vertical inner walls of the channel region, as taught by Shimizu. One having ordinary skill in the art is motivated to do so in order to, for example, implement a particular doping distribution across the structure, improving blocking voltage and decreasing ON resistance (see above).
Regarding claim 10, as shown above, Shimizu further teaches that a maximum doping concentration of the secondary channel regions is at least 50% higher than a minimum doping concentration of the first channel region, as explained above. The examiner notes that Shimizu does not teach that the other secondary channel region (to the right of the region labeled with A-A’ in FIG. 4) comprises a different doping profile than the doping profile taught by FIG. 5, thus one having ordinary skill in the art appreciates that the doping profile is the same.
It would have been obvious to one having ordinary skill in the art to further modify the semiconductor device taught by Treu and Shimizu such that a maximum doping concentration of the secondary channel regions is at least 50% higher than a minimum doping concentration of the first channel region, as taught by Shimizu. One having ordinary skill in the art is motivated to do so for at least the reasons stated above.
Regarding claim 21, Treu discloses the limitations of claim 20, as explained above. As further explained above, Shimizu teaches a first secondary channel region below a source region and doped with an n-type dopant which extends vertically into a central region of a channel region. Shimizu further teaches, in FIG. 11, a plurality of trenches TR and source regions SR therebetween. The examiner notes that this suggests to one of ordinary skill in the art that the aforementioned secondary channel structure can be implemented in the plural, in adjacent channel structures such as those taught by Treu.
It would have been obvious to one having ordinary skill in the art to modify the device taught by Treu such that both the first and second channel regions taught by Treu comprise a secondary channel region as taught by Treu. One having ordinary skill in the art would have been motivated to do so in order to, for example, achieve the benefits taught by Shimizu (see above) in two channel regions.
Regarding claim 22, Shimizu further teaches a secondary channel region with a maximum doping concentration that is at least 50% higher than a minimum doping concentration of a first channel region, as explained above. It would have been obvious to further modify the device taught by Treu and Shimizu such that the secondary channel regions have a maximum doping concentration that is at least 50% higher than a minimum doping concentration of the first channel region. One having ordinary skill in the art is motivated to do so in order to, for example, garner the benefits taught by Shimizu (see above) for two channel regions.
Regarding claim 23, Treu discloses the limitations of claim 20, as explained above. Treu does not teach secondary channel regions.
Shimizu teaches a pair of secondary channel regions doped with an n-type dopant and extending on vertical inner walls within a channel region. Also as shown above, Shimizu teaches, to one of ordinary skill in the art, that this structure can be used in multiple side-by-side trench and channel structures, such as those taught by Treu.
It would have It would have been obvious to modify the semiconductor device taught by Treu such that the first and second channel regions contain secondary channel regions which are n-typed doped and extend vertically into a central region of the first and second channel regions. One having ordinary skill in the art is motivated to do so in order to, for example, garner the benefits taught by Shimizu (see above) for two channel regions.
Regarding claim 24, Shimizu further teaches a maximum doping concentration in secondary channel regions which are at least 50% higher than a minimum doping concentration in a primary channel region. The examiner notes that, as stated above, Shimizu teaches one of ordinary skill in the art to employ this structure in the plural.
It would have been obvious to one of ordinary skill in the art to further modify the semiconductor device taught by Treu and Shimizu such that the first and second channel regions have maximum doping concentrations in the secondary channel regions which are at least 50% higher than a minimum doping concentration in the first channel regions. . One having ordinary skill in the art is motivated to do so in order to, for example, garner the benefits taught by Shimizu (see above) for two channel regions.
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Treu (US 20090068803 A1) in view of Shimizu (US 20100163935 A1) in further view of Alexandrov (US 20140361349 A1).
Regarding claim 16, Treu and Shimizu teach the limitations of claim 15, as explained above. Treu and Shimizu do not teach a dielectric material that fills portions of the first and second gate trenches.
Alexandrov teaches, in FIG. 3K, a series of source contacts, and gate contacts in trenches. In addition, these gate trenches are filled with “trench fill passivation” 312 (dielectric material), which isolate a first gate electrode from a first source electrode, and isolate a second gate electrode from a second source electrode.
It would have been obvious to one having ordinary skill in the art to modify the semiconductor device taught by Treu and Shimizu such that the first and second gate trenches were filled with a dielectric material which isolates the first gate and source electrodes and the second gate and source electrodes. One having ordinary skill in the art is motivated to do so in order to, for example, increase the reliability of the device by preventing a short between the gate and source electrodes.
Regarding claim 17, Alexandrov further teaches, in FIG. 4K, a ‘source metal overlay’ (first metal overlay) 313 over a ‘source contact’ (first source electrode) 219, a second source electrode (unlabeled), a first gate trench (trench wherein gate contact 211 is located), and a second gate trench (unlabeled). The examiner notes that although there is not an anode trench in FIG. 4K, Alexandrov teaches that the first metal overlay covers all of the top surface components in a device, which one having ordinary skill in the art would understand to include the anode trench taught by Treu.
It would have been obvious to one having ordinary skill in the art to further modify the semiconductor structure taught by Treu, Shimizu, and Alexandrov such that the top surface electrodes and trenches (including the first and second source electrodes, first and second gate trenches, and the anode trench) have a first metal overlay thereover, as taught by Alexandrov. One having ordinary skill in the art is motivated to do so in order to, for example, to provide an interconnect to the source electrode, as taught by Alexandrov (paragraph 0061).
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Treu (US 20090068803 A1) in view of Agarwal (US 20150084062 A1).
Regarding claim 18, as explained above, Treu discloses the limitations of claim 11. However, Treu does not teach a drift layer.
Agarwal teaches, in FIG. 5, a semiconductor device (called a Vertical Diffused MOSFET in the title) with a substrate 54 and a drift layer 66 above the substrate.
It would have been obvious to one having ordinary skill in the art to modify the semiconductor structure taught by Treu such that the body region further comprises a drift layer above the substrate with an n-type dopant, as taught by Agarwal. One having ordinary skill in the art is motivated to do so in order to, for example, spread the depletion region, raising the blocking voltage of the device in its OFF state.
Regarding claim 19, Agarwal further teaches, in FIG. 5, a “spreading layer” (current spreading layer) 68 above the drift layer.
It would have been obvious to one having ordinary skill in the art to further modify the semiconductor device taught by Treu and Alexandrov such that the device further comprises a current spreading layer above the drift layer. One having ordinary skill in the art is motivated to do so because, for example, in a device with a spreading layer: “the device allows the spreading layer to lower forward voltage drop across a diode, thus reducing leakage current of the device” (Agarwal, paragraph 4).
Claim(s) 25-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Treu (US 20090068803 A1) in view of McNutt (US 20080308838 A1).
Regarding claim 25, Treu teaches, in FIG. 2A, a semiconductor structure. Paragraph 0019 states “[a]lthough not illustrated in FIG. 1A, a drain contact would be provided on the bottom of the substrate when . . . completed” (drain cathode electrode and substrate), the examiner notes that although this does not directly refer to FIG. 2A, it is inherent that the VJFET of FIG. 2A (see paragraph 007) has a drain-cathode electrode below the substrate, by the definition of a VJFET (that is, that the source and drain must be opposite one another vertically). FIG. 2A further teaches body region 2 over the substrate comprising a top surface, and a source area 4 (first source region) extending into the body region from the top surface. FIG. 3A clarifies that the gate metallization 12a of FIG. 2A is in a U-shaped region (first gate trench, note the n+ region having two peaks, with the p+ doped trench therebetween). In addition, FIG, 2A discloses P doped region 14, which is in a U-shaped trench of its own, below the source region (anode region/anode trench). Paragraph 0025 teaches that the P+ doped portions of the anode “are short-circuited with the source-areas 4, thus forming the built-in PN-diode.” This discloses that the electrode 6 is continually formed onto the second source region (forming the anode trench). FIG. 2A discloses a source-metallization 6 (first source electrode), and a first gate electrode (unlabeled, labeled 12a in FIG 1A) over a portion of the first gate trench and between the first gate trench and the anode trench to the right thereof (see FIG. 3A); source electrode 6 extends into the anode trench, further defining the anode electrode, and electrically coupling the source and anode electrodes. The first gate region forms part of a first VJFET (see paragraph 0016) and the anode region forms part of a vertical diode cell (see paragraph 0025) that is coupled anti-parallel with the first vertical JFET cell (the p-doped anode to the anode electrode, and the n doped region 4 to the source electrode 12, in FIG. 2A, are anti-parallel).
Treu does not teach a MOSFET device coupled in series to the first source electrode of the first vertical JFET cell.
McNutt teaches, in paragraph 26, “For power switching applications, a VJFET may be used in a cascode configuration, in which a low-voltage normally-off (Noff) device is connected in series with a high-voltage "normally-on" (Non) device . . . the gate of the Non device is connected to the source of the Noff device . . . The cascode configuration has several advantages compared to a single device . . . [such as] an integral anti-parallel diode.”
McNutt does not explicitly teach the use of a MOSFET as a normally-off device in this anti-parallel cascode configuration.
Agarwal teaches, in FIG. 3, a “power MOSFET device” (paragraph 0030) which has source, drain, and gate electrodes (68, 70, and 66, respectively).
It would have been obvious to one having ordinary skill in the art to add a MOSFET in series with the semiconductor structure taught by Treu such that the drain electrode of the MOSFET taught by Agarwal is in series with the first source electrode of the first vertical JFET cell, as taught by McNutt. One having ordinary skill in the art is motivated to do so in order to, for example, create a device with “. . . reduced Miller capacitance; (ii) [and the] elimination of the need for a high-voltage Noff VJFETs, which can be very resistive” (McNutt, paragraph 0026).
Regarding claim 26, Treu further teaches, in FIG 3A, a second source region on the other side of the vertical diode cell in a plan view. The examiner notes that the second source region will exist on the top surface of the body region and will have all of the same elements below it as the first source region, as shown by FIG. 2A. This includes second u-shaped gate region having a portion below the second source region defining a second gate trench, a second portion of the anode region below the second source region such that the anode trench is between the first gate trench and the second gate trench, a second source electrode over the second source region and between the second gate trench and the anode trench, a second gate electrode over a portion of a bottom surface of the second gate trench, in
which the first electrode, second source electrode, and the anode electrode are electrically coupled, and where the second gate region forms part of a second vertical JFET cell located on the opposite side of the first vertical JFET cell from the vertical diode cell. The examiner notes that the Schottky diode between the first and second JFET cells are anti-parallel (as the current travels from the source to the anode, either right to left or left to right for the first or second JFET cell, respectively).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ryu (US 20040212011 A1): SiC MOSET with anti-parallel Schottky diodes.
Baliga (US 4967243 A): High-speed integral antiparallel Schottky diode.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.S.M./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights