DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 34-36, 38-42, and 44-54 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tran et al. (US 2017/0236869) (hereafter Tran).
Regarding claim 34, Tran discloses an integrated assembly, comprising:
a CMOS region 102 (Fig. 1a, paragraph 0018);
fins 115 (Fig. 1a, paragraph 0018) extending across the CMOS region 102 (Fig. 1a), the fins 115 (Fig. 1b) being on a first pitch (distance between 115 in Fig. 1b);
a circuit arrangement 105 (Fig. 1a, paragraph 0013) associated with the CMOS region 102 (Fig. 1a) and comprising segments of one or more of the fins 115 (Fig. 1a); and
conductive structures 110 (Fig. 1a, paragraph 0022), some of the conductive structures being electrically coupled with the circuit arrangement 105 (Fig. 1a) and the conductive structures 110 (Fig. 1a) being on a second pitch (distance between 110 in Fig. 1a) different from the first pitch (distance between 115 in Fig. 1b).
Regarding claim 35, Tran further discloses the integrated assembly of claim 34 wherein the circuit arrangement 105 (Fig. 1a) comprises a first dimension (region where 105 of 102 is formed in Fig. 1a) along a first direction (vertical direction in Fig. 1a) and wherein the conductive structures 110 (Fig. 1a, paragraph 0022) extend along a second direction (horizontal direction in Fig. 1a) substantially orthogonal to the first direction (vertical direction in Fig. 1a).
Regarding claim 36, Tran further discloses the integrated assembly of claim 35 wherein a second dimension (region where 105 of 104 is formed in Fig. 1a) being a distance across said some of the conductive structures 110 (Fig. 1a) along the first direction (vertical direction in Fig. 1a) wherein the second dimension (region where 105 of 104 is formed in Fig. 1a) is substantially the same as the first dimension (region where 105 of 102 is formed in Fig. 1a).
Regarding claim 38, Tran further discloses the integrated assembly of claim 35 wherein the circuit arrangement 105 (Fig. 1a, paragraph 0013) comprises a first (105 of 102 in Fig. 1a) and a second circuit arrangement (105 of 104 in Fig. 1a), the first circuit (105 of 102 in Fig. 1a) arrangement having a first dimension (region where 105 of 102 is formed in Fig. 1a) along the first direction (vertical direction in Fig. 1a), and the second circuit arrangement (105 of 104 in Fig. 1a) having a second dimension (region where 105 of 104 is formed in Fig. 1a) along the second direction (horizontal direction in Fig. 1a).
Regarding claim 39, Tran further discloses the integrated assembly of claim 35 wherein the fins 115 (Fig. 1a) extend along the first direction (vertical direction in Fig. 1a).
Regarding claim 40, Tran further discloses the integrated assembly of claim 35 wherein the fins 115 (Fig. 1a) extend along the second direction (horizontal direction in Fig. 1a).
Regarding claim 41, Tran further discloses the integrated assembly of claim 34 wherein the conductive structures 110 (Fig. 1a, paragraph 0022, wherein “wordlines”) are wordlines.
Regarding claim 42, Tran (applied different element for conductive structures as applied in the claim 34 in the above) discloses an integrated assembly, comprising:
a CMOS region 102 (Fig. 1a, paragraph 0018);
fins 115 (Fig. 1a, paragraph 0018) extending across the CMOS region 102 (Fig. 1a), the fins 115 (Fig. 1b) being on a first pitch (distance between 115 in Fig. 1b);
a circuit arrangement 105 (Fig. 1a, paragraph 0013) associated with the CMOS region 102 (Fig. 1a) and comprising segments of one or more of the fins 115 (Fig. 1a);
conductive structures 190 (Fig. 1a, paragraph 0014), some of the conductive structures 190 (Fig. 1a) being electrically coupled with the circuit arrangement 105 (Fig. 1a) and the conductive structures 190 (Fig. 1a) being on a second pitch (distance between 190 in Fig. 1a) different from the first pitch (distance between 115 in Fig. 1b); and
wherein the conductive structures 190 (Fig. 1a, paragraph 0014, wherein “bitline”) are digit lines.
Regarding claim 44, Tran further discloses the integrated assembly of claim 34 wherein the circuit arrangement 105 (Fig. 1a, paragraph 0013, wherein “sense amplifier”) comprises one or more SENSE AMPLIFIERS.
Regarding claim 45, Tran discloses an integrated assembly, comprising:
a CMOS region 102 (Fig. 1a, paragraph 0018);
fins 115 (Fig. 1a, paragraph 0018) extending across the CMOS region 102 (Fig. 1a),
a circuit arrangement 105 (Fig. 1a, paragraph 0013) associated with the CMOS region 102 (Fig. 1a) and comprising segments of one or more of the fins 115 (Fig. 1a);
the circuit arrangement 105 (Fig. 1a) having a first dimension (region where 105 of 102 is formed in Fig. 1a); and
conductive structures 110 (Fig. 1a, paragraph 0022), some of the conductive structures 110 (Fig. 1a) being electrically coupled with the circuit arrangement 105 (Fig. 1a);
a second dimension (region where 105 of 104 is formed in Fig. 1a) being a distance across said some of the conductive structures 110 (Fig. 1a);
the conductive structures 110 (Fig. 1a) being aligned with the circuit arrangement 105 (Fig. 1a) such that the second dimension (region where 105 of 104 is formed in Fig. 1a) is substantially the same as the first dimension (region where 105 of 102 is formed in Fig. 1a).
Regarding claim 46, Tran further discloses the integrated assembly of claim 45 wherein the fins 115 (Fig. 1a) are on a first pitch (distance between 115 in Fig. 1b) and wherein the conductive structures are on a second pitch (distance between 110 in Fig. 1a) different from the first pitch (distance between 115 in Fig. 1b).
Regarding claim 47, Tran further discloses the integrated assembly of claim 45 wherein the circuit arrangement 105 (Fig. 1a) comprises the first dimension (region where 105 of 102 is formed in Fig. 1a) along a first direction (vertical direction in Fig. 1a) and wherein the conductive structures 110 (Fig. 1a) extend along a second direction (horizontal direction in Fig. 1a) substantially orthogonal to the first direction (vertical direction in Fig. 1a).
Regarding claim 48, Tran further discloses the integrated assembly of claim 45 further comprising a second dimension (region where 105 of 104 is formed in Fig. 1a) being a distance across said some of the conductive structures 110 (Fig. 1a) along the first direction (vertical direction in Fig. 1a), wherein the second dimension (region where 105 of 104 is formed in Fig. 1a) is substantially the same as the first dimension (region where 105 of 102 is formed in Fig. 1a).
Regarding claim 49, Tran further discloses the integrated assembly of claim 47 wherein the fins 115 (Fig. 1a) extend along the first direction (vertical direction in Fig. 1a).
Regarding claim 50, Tran further discloses the integrated assembly of claim 47 wherein the fins 115 (Fig. 1a) extend along the second direction (horizontal direction in Fig. 1a).
Regarding claim 51, Tran further discloses the integrated assembly of claim 45 further comprising a second region (region where 105 of 104 is formed in Fig. 1a) proximate the CMOS region 102 (Fig. 1a) and wherein the conductive structures 110 (Fig. 1a) are associated with the second region (region where 105 of 104 is formed in Fig. 1a).
Regarding claim 52, Tran further discloses the integrated assembly of claim 51 wherein the second region (region where 105 of 104 is formed in Fig. 1a) is laterally offset relative to the CMOS region 102 (Fig. 1a).
Regarding claim 53, Tran further discloses the integrated assembly of claim 51 wherein the second region (region where 105 of 104 is formed in Fig. 1a) is vertically offset relative to the CMOS region 102 (Fig. 1a).
Regarding claim 54, Tran further discloses the integrated assembly of claim 51 wherein the second region (region where 105 of 104 is formed in Fig. 1a) is directly over the CMOS region 102 (Fig. 1a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 37 is rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. (US 2017/0236869) (hereafter Tran), in view of Mentovich et al. (US 2019/0074040) (hereafter Mentovich).
Regarding claim 37, Tran (applied different elements for a circuit arrangement and conductive structures as applied in the claim 34 in the above) discloses an integrated assembly, comprising:
a CMOS region 102 (Fig. 1a, paragraph 0018);
fins 115 (Fig. 1a, paragraph 0018) extending across the CMOS region 102 (Fig. 1a), the fins 115 (Fig. 1b) being on a first pitch (distance between 115 in Fig. 1b);
a circuit arrangement (105 and 110 in Fig. 1a, paragraph 0013) associated with the CMOS region 102 (Fig. 1a) and comprising segments of one or more of the fins 115 (Fig. 1a);
conductive structures 190 (Fig. 1a, paragraph 0014), some of the conductive structures 190 (Fig. 1a) being electrically coupled with the circuit arrangement (105 and 110 in Fig. 1a) and the conductive structures 190 (Fig. 1a) being on a second pitch (distance between 190 in Fig. 1a) different from the first pitch (distance between 115 in Fig. 1b); and
wherein the circuit arrangement comprises a WORDLINE DRIVER arrangement and a SENSE AMPLIFIER arrangement (paragraph 0013, wherein “sense amplifier”).
Tran does not disclose the circuit arrangement comprises one or more WORDLINE DRIVERS.
Mentovich discloses the circuit arrangement (“memory” in paragraph 0043) comprises one or more WORDLINE DRIVERS (“high-speed wordline drivers” in paragraph 0043).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tran to form the circuit arrangement comprises one or more WORDLINE DRIVERS, as taught by Mentovich, in order to enhance read speed.
Claim 43 is rejected under 35 U.S.C. 103 as being unpatentable over Tran as applied to claim 34 above, and further in view of Mentovich et al. (US 2019/0074040) (hereafter Mentovich).
Regarding claim 43, Tran discloses the integrated assembly of claim 34, however Tran does not disclose the circuit arrangement comprises one or more WORDLINE DRIVERS.
Mentovich discloses the circuit arrangement (“memory” in paragraph 0043) comprises one or more WORDLINE DRIVERS (“high-speed wordline drivers” in paragraph 0043).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tran to form the circuit arrangement comprises one or more WORDLINE DRIVERS, as taught by Mentovich, in order to enhance read speed.
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813