DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 4/13/2026 is acknowledged.
The applicant’s arguments (REMARKS, second paragraph in page 9), Tran does not disclose “the conductive structures being on a second pitch different from the first pitch” (Claim 34, Lines 7-8) since “Referring to Fig. 1b of Tran and measuring when the repeating pattern of the conductive structures (doped wells) 110 equals approximately 4.5 cm and a repeating pattern of fins 115 equals approximately 4.5 cm, the same and not different as recited by claim 34”, is persuasive such that and the current office action becomes non-final.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 45 and 47-54 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tran et al. (US 2017/0236869) (hereafter Tran).
Regarding claim 45, Tran discloses an integrated assembly, comprising:
a CMOS region 102 (Fig. 1a, paragraph 0018);
fins 115 (Fig. 1a, paragraph 0018) extending across the CMOS region 102 (Fig. 1a),
a circuit arrangement 105 (Fig. 1a, paragraph 0013) associated with (see paragraph 0013, wherein “The first region 102 is a memory or array region for accommodating a plurality of memory cells 105”) the CMOS region 102 (Fig. 1a) and comprising segments of one or more of the fins 115 (Fig. 1a);
the circuit arrangement 105 (Fig. 1a) having a first dimension (vertical length of 105 of 102 in Fig. 1a); and
conductive structures 110 (Fig. 1a, paragraph 0022), some of the conductive structures 110 (Fig. 1a) being electrically coupled with the circuit arrangement 105 (Fig. 1a);
a second dimension (vertical length of 105 of 104 in Fig. 1a) being a distance across said some of the conductive structures 110 (Fig. 1a);
the conductive structures 110 (Fig. 1a) being aligned with the circuit arrangement 105 (Fig. 1a) such that the second dimension (vertical length of 105 of 104 in Fig. 1a) is substantially the same as the first dimension (vertical length of 105 of 102 in Fig. 1a).
Regarding claim 47, Tran further discloses the integrated assembly of claim 45 wherein the circuit arrangement 105 (Fig. 1a) comprises the first dimension (vertical length of 105 of 102 in Fig. 1a) along a first direction (vertical direction in Fig. 1a) and wherein the conductive structures 110 (Fig. 1a) extend along a second direction (horizontal direction in Fig. 1a) substantially orthogonal to the first direction (vertical direction in Fig. 1a).
Regarding claim 48, Tran further discloses the integrated assembly of claim 45 further comprising a second dimension (vertical length of 105 of 104 in Fig. 1a) being a distance across said some of the conductive structures 110 (Fig. 1a) along the first direction (vertical direction in Fig. 1a), wherein the second dimension (vertical length of 105 of 104 in Fig. 1a) is substantially the same as the first dimension (vertical length of 105 of 102 in Fig. 1a).
Regarding claim 49, Tran further discloses the integrated assembly of claim 47 wherein the fins 115 (Fig. 1a) extend along the first direction (vertical direction in Fig. 1a).
Regarding claim 50, Tran further discloses the integrated assembly of claim 47 wherein the fins 115 (Fig. 1a) extend along the second direction (horizontal direction in Fig. 1a).
Regarding claim 51, Tran further discloses the integrated assembly of claim 45 further comprising a second region (region where 105 of 104 is formed in Fig. 1a) proximate the CMOS region 102 (Fig. 1a) and wherein the conductive structures 110 (Fig. 1a) are associated with the second region (region where 105 of 104 is formed in Fig. 1a).
Regarding claim 52, Tran further discloses the integrated assembly of claim 51 wherein the second region (region where 105 of 104 is formed in Fig. 1a) is laterally offset relative to the CMOS region 102 (Fig. 1a).
Regarding claim 53, Tran further discloses the integrated assembly of claim 51 wherein the second region (region where 105 of 104 is formed in Fig. 1a) is vertically offset relative to the CMOS region 102 (Fig. 1a).
Regarding claim 54, Tran further discloses the integrated assembly of claim 51 wherein the second region (region where 105 of 104 is formed in Fig. 1a) is directly over the CMOS region 102 (Fig. 1a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 46 is rejected under 35 U.S.C. 103 as being unpatentable over Tran as applied to claim 45 above, and further in view of Shieh et al. (US 2015/0147867) (hereafter Shieh).
Regarding claim 46, Tran discloses the integrated assembly of claim 45, however Tran does not disclose the fins are on a first pitch and wherein the conductive structures are on a second pitch different from the first pitch.
Shieh discloses the fins (810 of 230 in Fig. 13, paragraph 0029) are on a first pitch (P1 in Fig. 13, paragraph 0029) and wherein the conductive structures (upper portions of 210 of 230 in Fig. 13, paragraph 0011) are on a second pitch (pitch between the upper portion of 210 on the left hand side of 720 and the upper portion of 210 on the right hand side of 720 in Fig. 13) different from the first pitch (P1 in Fig. 13).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tran to form the fins are on a first pitch and wherein the conductive structures are on a second pitch different from the first pitch, as taught by Shieh, since different pitches (Shieh, paragraph 0029) may be needed for different device components, such as an input/output component, a logic circuit, or a static random-access memory (SRAM). In addition, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Furthermore, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 34-36, 38-42, and 44 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. (US 2017/0236869) (hereafter Tran), in view of Shieh et al. (US 2015/0147867) (hereafter Shieh).
Regarding claim 34, Tran discloses an integrated assembly, comprising:
a CMOS region 102 (Fig. 1a, paragraph 0018);
fins 115 (Fig. 1a, paragraph 0018) extending across the CMOS region 102 (Fig. 1a), the fins 115 (Fig. 1b) being on a first pitch (distance between 115 in Fig. 1b);
a circuit arrangement 105 (Fig. 1a, paragraph 0013) associated with (see paragraph 0013, wherein “The first region 102 is a memory or array region for accommodating a plurality of memory cells 105”) the CMOS region 102 (Fig. 1a) and comprising segments of one or more of the fins 115 (Fig. 1a); and
conductive structures 110 (Fig. 1a, paragraph 0022), some of the conductive structures being electrically coupled with the circuit arrangement 105 (Fig. 1a).
Tran does not disclose the conductive structures being on a second pitch different from the first pitch.
Shieh discloses the conductive structures (upper portions of 210 of 230 in Fig. 13) being on a second pitch (pitch between the upper portion of 210 on the left hand side of 720 and the upper portion of 210 on the right hand side of 720 in Fig. 13) different from the first pitch (P1 in Fig. 13, paragraph 0029).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tran to form the conductive structures being on a second pitch different from the first pitch, as taught by Shieh, since different pitches (Shieh, paragraph 0029) may be needed for different device components, such as an input/output component, a logic circuit, or a static random-access memory (SRAM). In addition, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Furthermore, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 35, Tran further discloses the integrated assembly of claim 34 wherein the circuit arrangement 105 (Fig. 1a) comprises a first dimension (region where 105 of 102 is formed in Fig. 1a) along a first direction (vertical direction in Fig. 1a) and wherein the conductive structures 110 (Fig. 1a, paragraph 0022) extend along a second direction (horizontal direction in Fig. 1a) substantially orthogonal to the first direction (vertical direction in Fig. 1a).
Regarding claim 36, Tran further discloses the integrated assembly of claim 35 wherein a second dimension (region where 105 of 104 is formed in Fig. 1a) being a distance across said some of the conductive structures 110 (Fig. 1a) along the first direction (vertical direction in Fig. 1a) wherein the second dimension (region where 105 of 104 is formed in Fig. 1a) is substantially the same as the first dimension (region where 105 of 102 is formed in Fig. 1a).
Regarding claim 38, Tran further discloses the integrated assembly of claim 35 wherein the circuit arrangement 105 (Fig. 1a, paragraph 0013) comprises a first (105 of 102 in Fig. 1a) and a second circuit arrangement (105 of 104 in Fig. 1a), the first circuit (105 of 102 in Fig. 1a) arrangement having a first dimension (region where 105 of 102 is formed in Fig. 1a) along the first direction (vertical direction in Fig. 1a), and the second circuit arrangement (105 of 104 in Fig. 1a) having a second dimension (region where 105 of 104 is formed in Fig. 1a) along the second direction (horizontal direction in Fig. 1a).
Regarding claim 39, Tran further discloses the integrated assembly of claim 35 wherein the fins 115 (Fig. 1a) extend along the first direction (vertical direction in Fig. 1a).
Regarding claim 40, Tran further discloses the integrated assembly of claim 35 wherein the fins 115 (Fig. 1a) extend along the second direction (horizontal direction in Fig. 1a).
Regarding claim 41, Tran further discloses the integrated assembly of claim 34 wherein the conductive structures 110 (Fig. 1a, paragraph 0022, wherein “wordlines”) are wordlines.
Regarding claim 42, Tran further discloses the integrated assembly of claim 34 wherein
the conductive structures 110 (Fig. 1a, paragraph 0014, wherein “bitlines”; and see paragraph 0014, wherein “the WLs and BLs may be interchangeable”) are digit lines.
Regarding claim 44, Tran further discloses the integrated assembly of claim 34 wherein the circuit arrangement 105 (Fig. 1a, paragraph 0013, wherein “sense amplifier”) comprises one or more SENSE AMPLIFIERS.
Claim 37 is rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. (US 2017/0236869) (hereafter Tran), in view of Mentovich et al. (US 2019/0074040) (hereafter Mentovich).
Regarding claim 37, Tran (applied different elements for a circuit arrangement and conductive structures as applied in the claim 34 in the above) discloses an integrated assembly, comprising:
a CMOS region 102 (Fig. 1a, paragraph 0018);
fins 115 (Fig. 1a, paragraph 0018) extending across the CMOS region 102 (Fig. 1a), the fins 115 (Fig. 1b) being on a first pitch (distance between 115 in Fig. 1b);
a circuit arrangement (105 and 110 in Fig. 1a, paragraph 0013) associated with the CMOS region 102 (Fig. 1a) and comprising segments of one or more of the fins 115 (Fig. 1a);
conductive structures 190 (Fig. 1a, paragraph 0014), some of the conductive structures 190 (Fig. 1a) being electrically coupled with the circuit arrangement (105 and 110 in Fig. 1a) and the conductive structures 190 (Fig. 1a) being on a second pitch (distance between 190 in Fig. 1a) different from the first pitch (distance between 115 in Fig. 1b); and
wherein the circuit arrangement comprises a SENSE AMPLIFIER arrangement (paragraph 0013, wherein “sense amplifier”).
Tran does not disclose the circuit arrangement comprises a WORDLINE DRIVER.
Mentovich discloses the circuit arrangement (“memory” in paragraph 0043) comprises a WORDLINE DRIVER (“high-speed wordline drivers” in paragraph 0043).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tran to form the circuit arrangement comprises a WORDLINE DRIVER, as taught by Mentovich, in order to enhance read speed.
Claim 43 is rejected under 35 U.S.C. 103 as being unpatentable over Tran in view of Shieh as applied to claim 34 above, and further in view of Mentovich et al. (US 2019/0074040) (hereafter Mentovich).
Regarding claim 43, Tran in view of Shieh discloses the integrated assembly of claim 34, however Tran and Shieh do not disclose the circuit arrangement comprises one or more WORDLINE DRIVERS.
Mentovich discloses the circuit arrangement (“memory” in paragraph 0043) comprises one or more WORDLINE DRIVERS (“high-speed wordline drivers” in paragraph 0043).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tran in view of Shieh to form the circuit arrangement comprises one or more WORDLINE DRIVERS, as taught by Mentovich, in order to enhance read speed.
Response to Arguments
1. Applicant's arguments filed 4/13/2026 have been fully considered.
2. The applicant argues (REMARKS, Page 8, Lines 7-25) that “The Office states "a circuit arrangement 105 (Fig. 1a, paragraph 0013) associated with the CMOS region 102 (Fig. 1a)." (pg. 2 of the action). A quick review of Fig. 1a of Tran instantly shows that the "a circuit arrangement 105" is associated with the memory region 102 and not the CMOS region as recited in claim 34. That is, the Office mislabels 102 as a CMOS region when Tran clearly states it is a memory region: The first region 102 is a memory or array region for accommodating a plurality of memory cells 105. (paragraph 0013 of Tran)…one or more logic components which serve as peripheral circuit disposed in the second region 104. In one embodiment, the one or more logic components include fin-type based CMOS devices. (paragraph 0018 of Tran) Accordingly, Tran fails to teach "a circuit arrangement associated with the CMOS region" as positively recited by claim 34.The additional art of record fails to teach this limitation of claim 34, and therefore, independent claims 34 is in allowable form.” However, Tran et al. (US 2017/0236869) disclose a circuit arrangement 105 (Fig. 1a, paragraph 0013) associated with (see paragraph 0013, wherein “The first region 102 is a memory or array region for accommodating a plurality of memory cells 105”) the CMOS region 102 (Fig. 1a) and comprising segments of one or more of the fins 115 (Fig. 1a).
3. The applicant argues (REMARKS, Page 10, Lines 1-18) that “A quick review of Fig. 1a of Tran instantly shows that the "a circuit arrangement 105" is associated with the memory region 102 and not the CMOS region as recited in claim 45. That is, the Office mislabels 102 as a CMOS region when Tran clearly states it is a memory region: The first region 102 is a memory or array region for accommodating a plurality of memory cells 105. (paragraph 0013 of Tran)…one or more logic components which serve as peripheral circuit disposed in the second region 104. In one embodiment, the one or more logic components include fin-type based CMOS devices. (paragraph 0018 of Tran) Accordingly, Tran fails to teach "a circuit arrangement associated with the CMOS region" as positively recited by claim 45. The additional art of record fails to teach this limitation of claim 45, and therefore, independent claims 45 is in allowable form.” However, Tran et al. (US 2017/0236869) disclose a circuit arrangement 105 (Fig. 1a, paragraph 0013) associated with (see paragraph 0013, wherein “The first region 102 is a memory or array region for accommodating a plurality of memory cells 105”) the CMOS region 102 (Fig. 1a) and comprising segments of one or more of the fins 115 (Fig. 1a).
4. The applicant argues (REMARKS, second last paragraph in page 10) that “The Office relies on Tran's teaching to circuit arrangement ("MTP RRAM cells" as defined by Tran) 105 and conductive structures 190 to teach this limitation. (pg. 2 of the action). However, MTP RRAM cells" as defined by Tran) 105 equals approximately 2.8 cm and the conductive structures 190 equal approximately 3.5 cm, completely different and not the same as recited by claim 45.” However, Tran et al. (US 2017/0236869) disclose the conductive structures 110 (Fig. 1a) being aligned with the circuit arrangement 105 (Fig. 1a) such that the second dimension (vertical length of 105 of 104 in Fig. 1a) is substantially the same as the first dimension (vertical length of 105 of 102 in Fig. 1a).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights