DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 7-12 objected to because of the following informalities: the claims state “The semiconductor device of any one of claim “number”” with reference only to one dependent previous claim number”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 and 8-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In the instant case, Claim 1 discloses “wherein the gate busbar comprises a plurality of first portions each disposed along a second axis and at least one second portion each disposed along the first axis, wherein the second axis intersects with the first axis”. It is not clear if the second portion comprises multiple portion or if any correlation with the first portion exists or even the geometric relationship between the first and second portions. Although the claims are interpreted broadly in light of the disclosure, however importing limitations from the disclosure is impermissible and the claims must stand on their own.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YAO et al. (CN-114220853), with an machine translated English version attached, (hereinafter, YAO).
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RE Claim 1, Yao discloses in FIGS. 1-4 a power semiconductor device having a plurality of cells, wherein each of the plurality of cells [abstract], comprises a gate, the semiconductor device comprising:
a gate pad 12, since the emitter pad is located on the same side as the gate pad, the presence of gate pad and gate line coincide with and below the emitter pad and emitter line;
a gate busbar 13 “annular gate bus”; and
a plurality of gate lines,
wherein the gate busbar connects the gate pad to the plurality of gate lines,
wherein the plurality of gate lines connects the gate busbar to the gates of the plurality of cells, and
wherein each of the plurality of gate lines is disposed along a first axis “y-axis”, which is implicitly met since the emitter pad is located on the same side as the gate pad, the presence of gate pad and gate line coincide with and below the emitter pad and emitter line,
wherein the gate busbar 13 comprises a plurality of first portions each disposed along a second axis x-axis, i.e. parallel to the gate pad 12, and at least one second portion each disposed along the first axis Y-axis, referring to FIGS. 1 and 4
wherein the second axis X-axis intersects with the first axis Y-axis, referring to FIGS. 1 and 4 above. Examiner notes that first and second portions in extending in the first and second directions have variable thickness portion in the vertical and horizontal directions, which is considered to meet the claimed limitation, and
wherein the plurality of first portions are spaced apart from each other, and wherein each of the plurality of first portions comprises a plurality of first sub-portions “different thicknesses portions”, and lengths of the plurality of first sub-portions and widths or thicknesses of the plurality of first sub-portions change with respective distances thereof from the gate pad 12, referring to FIGS. 1 and 4, so that gate signals arriving at the gates of the plurality of cells from the gate pad via the gate busbar and the plurality of gate lines are consistent [abstract]. Since The gate bus is far away from the gate pad, and the width of the gate bus is smaller. Thus, improving the consistency of the transmission of the gate signal on the gate bus, so as to improve the distance gate pad far away from the switch consistency between different cells, so as to improve the cell flow equalization, improving the robustness and reliability of the power chip, therefore, the claimed limitation is met.
RE Claim 7, Yao discloses a semiconductor device, wherein the at least one second portion connects the plurality of first portions to the gate pad, referring to FIG. 4, since the gate bus line 13 is continuous line with different thickness portions.
RE Claim 13, Yao discloses a semiconductor device, wherein the at least one second portion has a uniform width along the first axis, referring to FIG. 1.
RE Claim 14, Yao discloses a semiconductor device, wherein the gate pad 12 is located at a position selected from the group consisting of a corner, a middle of a side edge, and a middle region of the semiconductor device., referring to FISG.1 and 4. Since the gate pad 12 coincide and under the emitter pad 11, referring to Claim 1 rejection, the claimed limitation is met.
RE Claim 15, Yao discloses a semiconductor device, wherein the gate pad is located in a middle region of the semiconductor device, the gate busbar further comprises at least one third portion connected to ends of adjacent first portions at an edge of the semiconductor device, each third portion is disposed along the first axis; see fig. 4, third portion opposite second portion.
RE Claim 16, Yao discloses a semiconductor device, wherein the gate busbar further comprises a third portion connected to ends of the first portions at a side edge of the semiconductor device extending along the first axis, referring to FIG. 4, where the third portion opposite to second portion.
RE Claim 17, Yao discloses a semiconductor device, wherein the third portion has a width that changes along the first axis, referring to FIG. 4.
RE Claim 18, Yao discloses a semiconductor device, wherein the third portion “upper busbar line” 13 is provided with an opening, referring to FIG. 4.
Allowable Subject Matter
Claims 2-6 and 8-12 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In the instant case, HARRINGTON et al. (US 2022/0278212) disclose a semiconductor device comprising a semiconductor layer structure comprising an active area with a set of unit cell transistors and an inactive gate pad area. A gate resistor layer is provided on an upper side of the layer structure, and an inner contact is directly provided on the upper side. An outer contact is provided directly on upper side, where the outer contact encloses the inner contact within the inactive pad area in a horizontal cross-section of the device. An inner dielectric pattern is provided between the inner and outer contacts. A lumped gate resistor is defined in the gate layer directly underneath the pattern.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898