DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1a in the reply filed on April 13, 2026 is acknowledged.
Claim 9-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 13, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 12-13, and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shukh (US 20140353662 A1).
Regarding claim 1, Fig. 4 of Shukh discloses a semiconductor device (Fig. 4, memory cell 40, ¶ [0039]) comprising:
a first memory cell (Fig. 4, memory element MTJ2, ¶ [0037]) disposed on a first side of the semiconductor device (40) and connected to a transistor (Fig. 4, thin-film transistor TFT, ¶ [0033]); and
a second memory cell (Fig. 4, memory element MTJ1, ¶ [0037]) disposed on a second side of the semiconductor device (40) and connected to the transistor (TFT);
wherein the first side of the semiconductor device (40) is on top of the transistor (TFT) and the second side of the semiconductor device (40) is under the transistor (TFT).
Regarding claim 2, Fig. 4 of Shukh discloses the semiconductor device of claim 1 as applied above, and Fig. 4 of Shukh further discloses wherein:
the first memory cell (MTJ2) comprises a first magnetoresistive random access memory cell (“MTJ (or magnetoresistive (MR) element)”, ¶ [0009]) connected to a first bit line (Fig. 4, bit line BL2, ¶ [0037]); and
the second memory cell (MTJ1) comprises a second magnetoresistive random access memory cell (“MTJ (or magnetoresistive (MR) element)”, ¶ [0009]) connected to a second bit line (Fig. 4, bit line BL1, ¶ [0033]).
Regarding claim 3, Fig. 4 of Shukh discloses the semiconductor device of claim 1 as applied above, and Fig. 4 of Shukh further discloses wherein:
the transistor (TFT) comprises a source/drain region (Fig. 4, source region 34, drain region 35, ¶ [0033]);
the semiconductor device (40) further comprises a first source/drain contact (Fig. 4, contact 26, ¶ [0033]) disposed on a first side of the source/drain region (34, 35) on the first side of the semiconductor device (40), and a second source/drain contact (26) disposed on a second side of the source/drain region (34, 35) on the second side of the semiconductor device (40);
the first memory cell (MTJ2) is connected to the transistor (TFT) through the first source/drain contact (26); and
the second memory cell (MTJ1) is connected to the transistor (TFT) through the second source/drain contact (26).
Regarding claim 5, Fig. 4 of Shukh discloses the semiconductor device of claim 1 as applied above, and Fig. 4 of Shukh further discloses wherein the first side of the semiconductor device (40) comprises a frontside (top side in Fig. 4) of the semiconductor device (40), and the second side of the semiconductor device (40) comprises a backside (bottom side in Fig. 4) of the semiconductor device (40).
Regarding claim 12, Fig. 4 of Shukh discloses a semiconductor device (40) comprising:
a first magnetoresistive random access memory cell (MTJ2) disposed on a first side of the semiconductor device (40) and connected to a first side of a source/drain region (34, 35) of a transistor (TFT); and
a second magnetoresistive random access memory cell (MTJ1) disposed on a second side of the semiconductor device (40) and connected to a second side of the source/drain region (34, 35) of the transistor (TFT);
wherein the first side of the semiconductor device (40) is on top of the transistor (TFT) and the second side of the semiconductor device (40) is under the transistor (TFT); and
wherein the first side of the source/drain region (34, 35) corresponds to the first side of the semiconductor device (40), and the second side of the source/drain region (34, 35) corresponds to the second side of the semiconductor device (40).
Regarding claim 13, Fig. 4 of Shukh discloses the semiconductor device of claim 12 as applied above, and Fig. 4 of Shukh further discloses wherein the first side of the semiconductor device (40) comprises a frontside (top side in Fig. 4) of the semiconductor device (40), and the second side of the semiconductor device (40) comprises a backside (bottom side in Fig. 4) of the semiconductor device (40).
Regarding claim 17, Fig. 4 of Shukh discloses a semiconductor device (40) comprising:
a stacked structure comprising:
a transistor (TFT);
a first memory cell (MTJ2) stacked over the transistor (TFT); and
a second memory cell (MTJ1) stacked under the transistor (TFT);
wherein the transistor (TFT) is connected to the first memory cell (MTJ2) and to the second memory cell (MTJ1); and
wherein the first memory cell (MTJ2) is disposed on a first side of the semiconductor device (40) and the second memory cell (MTJ1) is disposed on a second side of the semiconductor device (40).
Regarding claim 18, Fig. 4 of Shukh discloses the semiconductor device of claim 17 as applied above, and Fig. 4 of Shukh further discloses wherein:
the transistor (TFT) comprises a source/drain region (34, 35);
the semiconductor device (40) further comprises a first source/drain contact (26) disposed on a first side of the source/drain region (34, 35) on the first side of the semiconductor device (40), and a second source/drain contact (26) disposed on a second side of the source/drain region (34, 35) on the second side of the semiconductor device (40);
the first memory cell (MTJ2) is connected to the transistor (TFT) through the first source/drain contact (26); and
the second memory cell (MTJ1) is connected to the transistor (TFT) through the second source/drain contact (26).
Regarding claim 19, Fig. 4 of Shukh discloses the semiconductor device of claim 17 as applied above, and Fig. 4 of Shukh further discloses wherein the first side of the semiconductor device (40) comprises a frontside (top side in Fig. 4) of the semiconductor device (40), and the second side of the semiconductor device (40) comprises a backside (bottom side in Fig. 4) of the semiconductor device (40).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Shukh (US 20140353662 A1) in view of Wang (US 20190386062 A1).
Regarding claim 4, Fig. 4 of Shukh discloses the semiconductor device of claim 1 as applied above, but Shukh fails to explicitly disclose wherein the transistor comprises a nanosheet transistor.
In the similar field of endeavor of memory cells, Fig. 3C of Wang discloses wherein the transistor (Fig. 3C, transistor 312, ¶ [0056]) comprises a nanosheet transistor (“Examples of semiconductor devices that can be formed in device layer 112 include, but are not limited to… nanowire FETs”, ¶ [0025]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to substitute the transistor of Shukh with the nanosheet transistor as disclosed by Wang. The claimed nanosheet transistor was known in the prior art and one skilled in the art could have combined the semiconductor device of Shukh with the nanosheet transistor of Wang with no change in their respective function, and the combination would have yielded the predictable result of creating memory cell. See KSR Internation Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claims 6-7, 11, 14-16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shukh (US 20140353662 A1) in view of Dutta et al. (US 20220254396 A1).
Regarding claim 6, Fig. 4 of Shukh discloses the semiconductor device of claim 1 as applied above, but Shukh fails to disclose comprising:
a first selector device corresponding to the first memory cell, wherein the first selector device is configured to permit current to flow from the first memory cell to the transistor when voltage applied to the first selector device is greater than or equal to a threshold activation voltage; and
a second selector device corresponding to the second memory cell, wherein the second selector device is configured to permit current to flow from the second memory cell to the transistor when voltage applied to the second selector device is greater than or equal to the threshold activation voltage.
In the similar field of endeavor of MRAM devices, Fig. 2 of Dutta discloses comprising:
a first selector device (Fig. 2, first selector device 140, ¶ [0062]) corresponding to the first memory cell (Fig. 2, MTJ 212, ¶ [0069]), wherein the first selector device (140) is configured to permit current to flow from the first memory cell (212) to the transistor (Fig. 2, transistor 136, ¶ [0058]) when voltage applied to the first selector device (140) is greater than or equal to a threshold activation voltage (“to activate the selector switch (also referred to as “closing” or “turning on” the selector switch), a voltage across the switch must be at least as large as a particular switch threshold Vs”, ¶ [0065]); and
a second selector device (Fig. 2, second selector device 144, ¶ [0062]) corresponding to the second memory cell (212), wherein the second selector device (144) is configured to permit current to flow from the second memory cell (212) to the transistor (136) when voltage applied to the second selector device (144) is greater than or equal to the threshold activation voltage (“to activate the selector switch (also referred to as “closing” or “turning on” the selector switch), a voltage across the switch must be at least as large as a particular switch threshold Vs”, ¶ [0065]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the memory cells of Shukh with the selector layers as disclosed by Dutta, to prevent unintended access to the other MRAM cell connected to a shared transistor during a read or write operation (see Dutta, ¶ [0046]).
Regarding claim 7, Shukh and Dutta together disclose the semiconductor device of claim 6 as applied above, but Shukh fails to disclose wherein:
the first selector device is disposed on the first side of the semiconductor device; and
the second selector device is disposed on the second side of the semiconductor device.
In the similar field of endeavor of MRAM devices, Fig. 2 of Dutta discloses wherein:
the first selector device (140) is disposed on the first side of the semiconductor device (100); and
the second selector device (144) is disposed on the second side of the semiconductor device (100).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the memory cells of Shukh with the selector layers as disclosed by Dutta, to prevent unintended access to the other MRAM cell connected to a shared transistor during a read or write operation (see Dutta, ¶ [0046]).
Regarding claim 11, Fig. 4 of Shukh discloses the semiconductor device of claim 1 as applied above, and Fig. 4 of Shukh further discloses wherein:
the transistor (TFT) is a shared transistor (“MTJ1 and MTJ2 connected to the same transistor TFT”, ¶ [0039]).
Shukh fails to disclose a top electrode of the first memory cell is connected to a first transistor different from the shared transistor through a first conductive line on the first side of the semiconductor device; and
a top electrode of the second memory cell is connected to a second transistor different from the first transistor and the shared transistor through a second conductive line on the second side of the semiconductor device.
In the similar field of endeavor of MRAM devices, Fig. 2 of Dutta discloses a top electrode (Fig. 2, top electrode 204, ¶ [0069]) of the first memory cell (212) is connected to a first transistor (Fig. 2, first transistor 128, ¶ [0070]) different from the shared transistor (136) through a first conductive line (Fig. 2, bit line 120, ¶ [0070]) on the first side of the semiconductor device (100); and
a top electrode (204) of the second memory cell (212) is connected to a second transistor (Fig. 2, second transistor 132, ¶ [0071]) different from the first transistor (128) and the shared transistor (136) through a second conductive line (Fig. 2, second bit line 124, ¶ [0071]) on the second side of the semiconductor device (100).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the memory cells of Shukh with the first and second transistors as disclosed by Dutta, to allow read and write currents to travel to specific locations within the array (see Dutta, ¶ [0061]).
Regarding claim 14, Fig. 4 of Shukh discloses the semiconductor device of claim 12 as applied above, but Shukh fails to disclose comprising:
a first selector device corresponding to the first magnetoresistive random access memory cell, wherein the first selector device is configured to permit current to flow from the first magnetoresistive random access memory cell to the transistor when voltage applied to the first selector device is greater than or equal to a threshold activation voltage; and
a second selector device corresponding to the second magnetoresistive random access memory cell, wherein the second selector device is configured to permit current to flow from the second magnetoresistive random access memory cell to the transistor when voltage applied to the second selector device is greater than or equal to the threshold activation voltage.
In the similar field of endeavor of MRAM devices, Fig. 2 of Dutta discloses comprising:
a first selector device (140) corresponding to the first magnetoresistive random access memory cell (212), wherein the first selector device (140) is configured to permit current to flow from the first magnetoresistive random access memory cell (212) to the transistor (136) when voltage applied to the first selector device (140) is greater than or equal to a threshold activation voltage (“to activate the selector switch (also referred to as “closing” or “turning on” the selector switch), a voltage across the switch must be at least as large as a particular switch threshold Vs”, ¶ [0065]); and
a second selector device (144) corresponding to the second magnetoresistive random access memory cell (212), wherein the second selector device (144) is configured to permit current to flow from the second magnetoresistive random access memory cell (212) to the transistor (136) when voltage applied to the second selector device (144) is greater than or equal to the threshold activation voltage (“to activate the selector switch (also referred to as “closing” or “turning on” the selector switch), a voltage across the switch must be at least as large as a particular switch threshold Vs”, ¶ [0065]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the memory cells of Shukh with the selector layers as disclosed by Dutta, to prevent unintended access to the other MRAM cell connected to a shared transistor during a read or write operation (see Dutta, ¶ [0046]).
Regarding claim 15, Shukh and Dutta together disclose the semiconductor device of claim 14 as applied above, but Shukh fails to disclose wherein:
the first selector device is disposed on the first side of the semiconductor device and is aligned with at least a bottom electrode of the first magnetoresistive random access memory cell;
and the second selector device is disposed on the second side of the semiconductor device and is aligned with at least a bottom electrode of the second magnetoresistive random access memory cell.
In the similar field of endeavor of MRAM devices, Fig. 2 of Dutta discloses wherein:
the first selector device (140) is disposed on the first side of the semiconductor device (100) and is aligned with at least a bottom electrode (208) of the first magnetoresistive random access memory cell (212); and
the second selector device (144) is disposed on the second side of the semiconductor device (100) and is aligned with at least a bottom electrode (208) of the second magnetoresistive random access memory cell (212).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the memory cells of Shukh with the selector layers as disclosed by Dutta, to prevent unintended access to the other MRAM cell connected to a shared transistor during a read or write operation (see Dutta, ¶ [0046]).
Regarding claim 16, Fig. 4 of Shukh discloses the semiconductor device of claim 12 as applied above, and Fig. 4 of Shukh further discloses wherein:
the transistor (TFT) is a shared transistor (“MTJ1 and MTJ2 connected to the same transistor TFT”, ¶ [0039]).
Shukh fails to disclose a top electrode of the first magnetoresistive random access memory cell is connected to a first transistor different from the shared transistor through a first conductive line on the first side of the semiconductor device; and
a top electrode of the second magnetoresistive random access memory cell is connected to a second transistor different from the first transistor and the shared transistor through a second conductive line on the second side of the semiconductor device.
In the similar field of endeavor of MRAM devices, Fig. 2 of Dutta discloses wherein:
the first selector device (140) is disposed on the first side of the semiconductor device (100) and is aligned with at least a bottom electrode (208) of the first magnetoresistive random access memory cell (212); and
the second selector device (144) is disposed on the second side of the semiconductor device (100) and is aligned with at least a bottom electrode (208) of the second magnetoresistive random access memory cell (212).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the memory cells of Shukh with the selector layers as disclosed by Dutta, to prevent unintended access to the other MRAM cell connected to a shared transistor during a read or write operation (see Dutta, ¶ [0046]).
Regarding claim 20, Fig. 4 of Shukh disclose the semiconductor device of claim 17 as applied above, and Fig. 4 of Shukh further discloses wherein:
the transistor (TFT) is a shared transistor (“MTJ1 and MTJ2 connected to the same transistor TFT”, ¶ [0039]).
Shukh fails to disclose a top electrode of the first memory cell is connected to a first transistor different from the shared transistor through a first conductive line on the first side of the semiconductor device; and
a top electrode of the second memory cell is connected to a second transistor different from the first transistor and the shared transistor through a second conductive line on the second side of the semiconductor device.
In the similar field of endeavor of MRAM devices, Fig. 2 of Dutta discloses a top electrode (204) of the first memory cell (212) is connected to a first transistor (128) different from the shared transistor (136) through a first conductive line (120) on the first side of the semiconductor device (100); and
a top electrode (204) of the second memory cell (212) is connected to a second transistor (132) different from the first transistor (128) and the shared transistor (136) through a second conductive line (124) on the second side of the semiconductor device (100).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the memory cells of Shukh with the first and second transistors as disclosed by Dutta, to allow read and write currents to travel to specific locations within the array (see Dutta, ¶ [0061]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Shukh (US 20140353662 A1) and Dutta (US 20220254396 A1) in further view of Ha (US 20230133638 A1).
Regarding claim 8, Shukh and Dutta together disclose the semiconductor device of claim 6 as applied above, but Shukh fails to disclose wherein:
the first selector device is disposed between a bottom electrode of the first memory cell and a bottom electrode contact corresponding to the first memory cell, and is self-aligned with the bottom electrode of the first memory cell; and
the second selector device is disposed between a bottom electrode of the second memory cell and a bottom electrode contact corresponding to the second memory cell, and is self-aligned with the bottom electrode of the second memory cell.
In the similar field of endeavor of MRAM devices, Fig. 2 of Dutta discloses wherein:
the first selector device (140) is disposed between a bottom electrode (Fig. 2, bottom electrode 208, ¶ [0069]) of the first memory cell (212) and a bottom electrode contact (Fig. 2, bottom contact 228, ¶ [0090]) corresponding to the first memory cell (212), and is aligned with the bottom electrode (208) of the first memory cell (212); and
the second selector device (144) is disposed between a bottom electrode (208) of the second memory cell (212) and a bottom electrode contact (228) corresponding to the second memory cell (212), and is aligned with the bottom electrode (208) of the second memory cell (212).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the memory cells of Shukh with the selector layers as disclosed by Dutta, to prevent unintended access to the other MRAM cell connected to a shared transistor during a read or write operation (see Dutta, ¶ [0046]).
Dutta fails to explicitly disclose that the selector layers are self-aligned.
In the similar field of endeavor of memory cells, Fig. 2E of Ha discloses the selector layers (Fig. 2E, selector layer 224, ¶ [0061]) are self-aligned (“the selector layer 224 may be formed by ion implantation and self-aligning without an additional patterning process”, ¶ [0072]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the memory cells of Shukh with the selector layers being self-aligned as disclosed by Ha, to prevent damage to other layers (see Ha, ¶ [0074]).
Conclusion
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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