DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Preliminary Amendment
Claims 2, 4, 6, 9, 13 and 17 have been amended; claims 1-23 are currently pending.
Information Disclosure Statement
The information disclosure statement filed on 6/02/2026 has been acknowledged and a signed copy of the PTO-1449 is attached herein.
Response to Terminal Disclaimer
The Terminal Disclaimer filed on 6/02/2026 has been reviewed and is accepted. The Terminal Disclaimer has been recorded. Accordingly, the rejection of claim s 1-23 on the ground of nonstatutory double patenting is hereby withdrawn.
Claim Objections
Claim 7, 18 are objected to because of the following informalities:
Claim 7 lines 2-3: “a layer of the thermal dissipation material… the thin layer of the thermal dissipation material” should be corrected as “
Claim 9 line 3: should be corrected as “…from a position adjacent to the circuit element…”,
Claim 18 line 5: should be corrected as “the vertical heat dissipation column “is” connected to …” and
Claim 22 line 3-4: should be corrected as “a metal plug is formed within “a concave” and “contacting” to the top…”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 13, 16 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by et al. (US 2004/0022102 A1, hereinafter “Liang”).
In regards to claim 1, Liang discloses (See, for example, Figs. 1-6) a device structure, comprising:
a semiconductor substrate (100) with an original semiconductor surface;
a circuit element (See Par [0037], Fig. 6) located within a semiconductor body region (gate 140, gate oxide 170, and diffusion region 160) of the semiconductor substrate (100); and
a vertical heat dissipation column (column filled in trench 150, See Fig. 1 and 6) in the semiconductor substrate (100) and surrounding the semiconductor body region (gate 140, gate oxide 170, and diffusion region 160);
wherein the vertical heat dissipation column (column filled in trench 150, See Fig. 1 and 6) comprises a thermal dissipation material (130) with a thermal conductivity (1.8 W/cmK, See Par [0038]) higher than that of the semiconductor substrate or that of silicon oxide (SiO2 0.014W/cm.K).
In regards to claim 2, Liang discloses (See, for example, Figs. 7-9) wherein the semiconductor substrate (100) comprises an edge region remote from the circuit element (See Par [0037], Fig. 6), and the vertical heat dissipation column (column filled in trench 150, See Fig. 1 and 6; See also Par [0043]) extends from a position adjacent to the circuit element (See Par [0037], Fig. 6) to another position close to the edge region (210/220) of the semiconductor substrate.
In regards to claim 3, Liang discloses (See, for example, Figs. 1-6) wherein the thermal dissipation material is BN, AlN, or metal (See, Par [0034]).
In regards to claim 13, Liang discloses (See, for example, Figs. 7-9) wherein the semiconductor substrate (100) comprises an edge region (210/220) remote from the circuit element (See Par [0037], Fig. 6), and the vertical heat dissipation column (column filled in trench 150, See Fig. 1 and 6; See also Par [0043]) extends from a position adjacent to the circuit element (See Par [0037], Fig. 6) to another position close to the edge region (210/220) of the semiconductor substrate, and a heat-dissipation sink (190) is connected to the vertical heat dissipation column column (column filled in trench 150, See Fig. 1 and 6; See also Par [0043]) close to the edge region (120/220) of the semiconductor substrate through an opening (where 190 is vertically connected to 130) above the vertical heat dissipation column (column filled in trench 150, See Fig. 1 and 6; See also Par [0043]).
In regards to claim 16, Liang discloses (See, for example, Figs. 7-8) a device structure, comprising:
a semiconductor substrate (for example, 100) with an original semiconductor surface;
a first transistor (six transistors 230) located within a first semiconductor body region (see Fig. 6) of the semiconductor substrate;
a second transistor (six transistors 230) located within a second semiconductor body region of the semiconductor substrate,
wherein the second transistor is remote from, rather than next to, the first transistor (one can choose two remotely placed transistors among the six transistors 230); and
a vertical heat dissipation column (130) in the semiconductor substrate,
wherein the vertical heat dissipation column (a column formed inside trench 150) comprises a thermal dissipation material (130) with a thermal conductivity (1.8 W/cmK, See Par [0038]) higher than that of the semiconductor substrate or that of silicon oxide (SiO2 0.014W/cm.K); and
wherein the vertical heat dissipation column extends from the first semiconductor body region to the second semiconductor body region (130 forms a continuous filled thermal conduction network across the chip, See Fig. 7).
In regards to claim 17, Liang discloses (See, for example, Fig. 7-8) the semiconductor substrate comprises an edge region (for example, 2310/220) remote from the first transistor (six transistors 230) and the second transistor (six transistors 230), and the vertical heat dissipation column (a column formed inside trench 150) further extends close to the edge region of the semiconductor substrate (lines 210/220 with contacts 215 carrying heat to ann external heat sink, See Fig. 8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-12 are rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Dahlstrom et al. (US 2012/0146098 A1, hereinafter Dahlstrom”).
In regards to claims 4-5, 7-8, and 10-11, Liang discloses all limitations of claim 1 above except wherein the vertical heat dissipation column comprises a layer of the thermal dissipation material and a thermal conductivity column covering the layer of the thermal dissipation material (claim 4); wherein the thermal conductivity column comprises metal (claim 5); wherein the vertical heat dissipation column comprises a layer of the thermal dissipation material and an isolation column covering the thin layer of the thermal dissipation material(claim 7); and wherein the isolation column comprises silicon oxide (claim 8); further comprising a shallow trench isolation (STI) region surrounding the semiconductor body region, wherein the vertical heat dissipation column is within the STI region (claim 10); and wherein the circuit element is a transistor, a resistor, a capacitor, a diode, or an inductor (claim 11)
Dahlstrom discloses (See, for example, Figs. 4-5) that wherein the vertical heat dissipation column (50) comprises a layer of the thermal dissipation material (45) and a thermal conductivity column (50) covering the layer of the thermal dissipation material (45); wherein the thermal conductivity column (50) comprises metal (See, Par [0022); the vertical heat dissipation column (50) comprises a layer of the thermal dissipation material (45) and an isolation column (15) covering the thin layer of the thermal dissipation material (45); and wherein the isolation column (15) comprises silicon oxide (See, Par [0016]); a shallow trench isolation (STI) region (15a/15b, Fig. 10) surrounding the semiconductor body region, wherein the vertical heat dissipation column (50) is within the STI region (See for example, 15a); wherein the circuit element is a transistor, a resistor, a capacitor, a diode, or an inductor (“ 25 comprises a interlevel dielectric (ILD) layer composed of BPSG in which contacts are formed to provide electrical connection to one or more devices (e.g., transistors, resistors, capacitors, etc.) formed in and/or on the substrate 10”, See, Par [0018]) .
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Liang by Dahlstrom because this would help the liner supply the electrical isolation while the core is selected purely for thermal performance permitting a metal core of substantially higher conductivity to reduce the thermal resistance of the trench isolation and thereby provides enhanced heat transfer away from the adjacent device.
In regards to claim 6, Liang as modified above discloses (See, for example, Figs. 7-9) wherein the semiconductor substrate (100) comprises an edge region (210/220) remote from the circuit element (See Par [0037], Fig. 6), and the layer of the thermal dissipation material (120) extends from a positon adjacent to the circuit element (See Par [0037], Fig. 6) to another position (this could be chip-wide network reaching contact s 215/217 too) close to the edge region (210/220) of the semiconductor substrate (100).
In regards to claim 9, Liang as modified above discloses (See, for example, Figs. 7-9) wherein the semiconductor substrate (100) comprises an edge region (210/220) remote from the circuit element (See Par [0037], Fig. 6), and the layer of the thermal dissipation material (120) extends from a positon adjacent or next to the circuit element (See Par [0037], Fig. 6) to another position (this could be chip-wide network reaching contact s 215/217 too) close to the edge region (210/220) of the semiconductor substrate (100).
In regards to claim 12, Liang as modified above discloses (See, for example, Figs. 1-6) wherein the transistor is a fin-structured transistor, a planar transistor, a GAA transistor, or a sheet transistor (planar transistor gate 140 over gate oxide 170 with diffusion regions 160, See Par [0037] and Fig. 6).
Claims 18-21 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Gambino et al. (US 2015/0091129 A1, hereinafter “Gambino”).
In regards to claims 18-21 and 23, Liang discloses all limitations of claim 16 above except further comprising: a first horizontal heat dissipation plate right under the first transistor; and a second horizontal heat dissipation plate right under the second transistor; wherein the vertical heat AlN dissipation column connected to or thermally coupled to both the first horizontal heat dissipation plate and the second horizontal heat dissipation plate; and wherein the first horizontal heat dissipation plate and/or the second horizontal heat dissipation plate comprises another thermal dissipation material with another thermal conductivity higher than that of the semiconductor substrate or that of silicon oxide (claim 18); wherein the thermal dissipation material and/or the another thermal dissipation material is BN, AlN or metal (claim 19); and : the first horizontal heat dissipation plate is connected to or thermally coupled to bottom surfaces of a drain region and a source region of the first transistor, and the first horizontal heat dissipation plate is connected to the vertical heat dissipation column; and the second horizontal heat dissipation plate is connected to or thermally coupled to bottom surfaces of a drain region and a source region of the second transistor, and the second horizontal heat dissipation plate is connected to the vertical heat dissipation column(claim 20); further comprising a shallow trench isolation (STI) region, wherein the vertical beat dissipation column is within the STI region (claim 21); and wherein the first horizontal heat dissipation plate and/or the second horizontal heat dissipation plate further comprises a thin oxide layer covering the another thermal dissipation material (claim 23)
Gambino while disclosing a microfabrication of a semiconductor devices teach (See, for example, Figs. 5-7) a first horizontal heat dissipation plate (124) right under the first transistor; and a second horizontal heat dissipation plate (124 extends from and connects to two or more of columns 22---four trenches 110 on a rectangle around the active area 10, See Fig. 6) right under the second transistor; wherein the vertical heat dissipation column connected to or thermally coupled to both the first horizontal heat dissipation plate and the second horizontal heat dissipation plate (124 extends from and connects to two or more of columns 22---four trenches 110 on a rectangle around the active area 10, See Fig. 6); wherein the first horizontal heat dissipation plate and/or the second horizontal heat dissipation plate comprises another thermal conductivity higher than that of the semiconductor substrate or that of silicon oxide (“a thermal conductivity of the structure material should have thermal conductivity greater than that of silicon dioxide,”, See for example, Par [0032]); wherein the thermal dissipation material and/or the another thermal dissipation material is BN, AlN or metal (See, for example, Pars [0032] and 33); and : 2112the first horizontal heat dissipation plate is connected to or thermally coupled to bottom surfaces of a drain region and a source region of the first transistor (lateral portion 124 lies beneath the whole active area 10, in which the FET source/drain are formed, and extends from columns 122); the first horizontal heat dissipation plate is connected to the vertical heat dissipation column; and the second horizontal heat dissipation plate is connected to or thermally coupled to bottom surfaces of a drain region and a source region of the second transistor, and the second horizontal heat dissipation plate is connected to the vertical heat dissipation column (“a lateral portion 124 of structure material can be formed extending from at least one column 122 substantially parallel to target layer 124”, See Par [0031]); further comprising a shallow trench isolation (STI) region (12), wherein the vertical beat dissipation column (122) is within the STI region (12); and wherein the first horizontal heat dissipation plate and/or the second horizontal heat dissipation plate (See, for example, 124) further comprises a thin oxide layer (211) covering the another thermal dissipation material (122).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Liang by Gambino because this would help enlarge the lateral portion’s area of contact with the underlying layer, thereby enhancing heat transfer from each column, and acts as a heat sink that holds the active area at a lower temperature during periods of elevated heat output.
Allowable Subject Matter
Claims 14-15 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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