DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Preliminary Amendment
Claims 2, 4, 6, 9, 13 and 17 have been amended; claim s1-23 are currently pending.
Information Disclosure Statement
The information disclosure statements filed on 11/26/2024, 7/9/2025, 10/30/2025, and 1/28/2026 have been acknowledged and signed copies of the PTO-1449 are attached herein.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1is rejected on the ground of non-statutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 18/534960.
Although the conflicting claims are not identical, they are not patentably distinct because they are drawn to different components of the single monolithic device structure disclosed in both specifications. The variation between claiming the "vertical column" (in the 18/534720 application) versus the "horizontal plate" (in the 18/534960 application) is considered an obvious variation or a minor modification of the same inventive concept, particularly when both components are disclosed as operating together to achieve the same result (efficient heat removal).
The table below illustrates why Claim 1 of the 18/533720 application is obvious in view of Claim 1 of the 18/534960 application.
Element
Claim 1 of 18/533720
Claim 1 of 18/534960
Obviousness Analysis
Preamble
A semiconductor device structure...
A semiconductor device structure...
Both applications are directed to the identical field of endeavor and share the exact same specification text and figures.
Substrate
...comprising a semiconductor substrate with an original semiconductor surface...
...comprising a semiconductor substrate with an original semiconductor surface...
Identical. Both structures are built upon the same P-type silicon substrate base.
Circuit Element
...a circuit element located within a semiconductor body region...
...a circuit element located within a semiconductor body region...
Identical. Both involve a transistor or circuit element formed in the active region.
Heat Removal Element (The Difference)
...and a vertical heat dissipation column in the semiconductor substrate and surrounding the semiconductor body region...
...and a horizontal heat dissipation plate in the semiconductor substrate and under the circuit element...
Not Patentably Distinct.
While 18533720 claims the "vertical column" and 18534960 claims the "horizontal plate", the specification teaches that these are merely two parts of the same integral heat dissipation network.
Figures 8b and 9b in both applications show the "Vertical Heat-Dissipation Column (VHDC)" and "Horizontal Heat-Dissipation Plate (HHDP)" physically connected. It would be obvious to one of ordinary skill in the art to add the vertical column of 18533720 to the device of '960 because the 18534960 specification itself discloses forming them simultaneously (Fig. 1, Step 40).
Material Properties
...wherein the vertical... column comprises a thermal dissipation material with a thermal conductivity higher than that of the semiconductor substrate...
...wherein the horizontal... plate comprises a first thermal dissipation material with a first thermal conductivity higher than the thermal conductivity of the semiconductor substrate...
Identical Properties.
Both claims require a high-thermal-conductivity material (e.g., higher than silicon/oxide). The material choice does not render the claims distinct.
Therefore, it would have been obvious to a person of ordinary skill in the art to modify the device claimed in the 18/534960 application (having a horizontal plate) to include the features claimed in the 18/533720 application (the vertical column). In the common specification of both applications. The fabrication method (e.g., Fig. 1, STEP 40 in 18/533720 and Fig. 1, STEP 40 in 18/534960) describes a single process flow: "Remove the vertical spacer, form Horizontal Heat-Dissipation Plate (HHDP)... and form Vertical Heat-Dissipation Column (VHDC)". Because the single disclosed embodiment inherently possesses both features, the applicant is effectively attempting to secure two patents for the same device by reciting the "vertical" feature in one application and the "horizontal" feature in the other. This extends the patent term for the same invention unjustifiably.
Claim 1 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 19/210377.
The conflicting claims are not patentably distinct because they claim the same apparatus using slightly different terminology. Both applications describe a structure where a heat-dissipating material is embedded within the isolation region (STI) surrounding the active devices. The 18/533720 application refers to this as a "vertical heat dissipation column," while the 18/210377 application refers to it as a "heat removing layer" within a "composite STI region." These are obvious variations of the same inventive concept.
The table below details the overlap between the claims, demonstrating why the instant claim is obvious in view of the reference claim.
Element
Claim 1 of 18/533720
Claim 1 of 19/210377
Obviousness Analysis
Preamble
A semiconductor device structure...
A semiconductor circuit structure...
Identical Field. Both are directed to semiconductor structures with integral heat removal.
Substrate
...comprising a semiconductor substrate with an original semiconductor surface...
...comprising a semiconductor substrate with an original semiconductor surface...
Identical.
Active Region
...a circuit element located within a semiconductor body region...
...a set of active regions [or transistors] within the semiconductor substrate...
Not Patentably Distinct.
A "circuit element" in a "semiconductor body" is functionally equivalent to an "active region" containing transistors.
Isolation / Heat Structure
...and a vertical heat dissipation column in the semiconductor substrate and surrounding the semiconductor body region...
...and a composite STI region surrounding the set of active regions... wherein the composite STI region includes a heat removing layer...
Structurally Equivalent.
The '720 application claims a "column" surrounding the body. The '377 application claims a "heat removing layer" inside the STI that surrounds the active region.
Since the "vertical column" in '720 is formed within the STI region (see '720 Spec, Step 300: "form Vertical Heat-Dissipation Column (VHDC) within the STI region"), it is structurally identical to the "heat removing layer" inside the "composite STI region" of '377. The change in nomenclature does not create a patentable distinction.
Material Properties
...wherein the vertical... column comprises a thermal dissipation material with a thermal conductivity higher than that of the semiconductor substrate or that of silicon oxide.
...wherein the material of the heat removing layer is different from SiO2 [and specified as higher conductivity .
Obvious / Overlapping.
Claim 1 of '377 requires the material to be different from SiO2. The specification of '377 further clarifies (and dependent claims confirm) that this material is selected for high thermal conductivity (e.g., Silicon or other high-k materials).
It would be obvious to select a material with higher thermal conductivity than oxide for the "heat removing layer" of '377 to achieve the stated goal of "direct die heat removal," rendering the specific limitation in '720 obvious over '377.
The "vertical heat dissipation column" claimed in the 18/533720 application is effectively the same structure as the "heat removing layer" in the "composite STI" claimed in the 18/210377 application. Both structures are located in the isolation trench surrounding the active device and serve the identical function of heat dissipation. Therefore, the claims are not patentably distinct.
Claim 1 is rejected on the ground of non-statutory double patenting as being unpatentable over the claims of the following co-pending applications US 18/980,888, US 18/674,649, and US 19/308,894.
Although the conflicting claims are not identical, they differ only in obvious variations or scope breadth. The core inventive concept—utilizing a structure within the Shallow Trench Isolation (STI) region comprising a material with higher thermal conductivity than silicon oxide to remove heat—is present in all applications.
The following table contrasts the subject matter of the instant application (based on the specification and abstract provided, which define the "Vertical Heat Dissipation Column") with the specific independent claims of the cited co-pending applications.
Feature/Element
US 18/533,720 (Claim 1)
US 18/980,888 (e.g., Claim 21)
US 18/674,649 (e.g., Claim 26)
US 19/308,894 (e.g., Claim 1+11, 1+9)
Obviousness Analysis
Core Structure
Semiconductor substrate with a circuit element and a vertical heat dissipation column (VHDC) in the substrate.
Recites a semiconductor substrate with active regions and a first STI region extending along a first direction.
Recites a semiconductor substrate with
active regions and a first STI region.
Recites a semiconductor substrate with active regions and a first STI region.
The "Vertical Heat Dissipation Column" of '720 is structurally equivalent to the "STI region" modified for heat removal in the references. An STI trench is inherently a vertical structure in the substrate.
Heat Removal Element
VHDC comprises a material with thermal conductivity higher than SiO2 or the substrate.
STI region includes a heat removing layer; thermal conductivity is higher than SiO2.
STI region includes a heat removing layer;
thermal conductivity is higher than SiO2.
STI region includes a heat removing layer; material is different from SiO2 (implies higher conductivity contextually).
The limitation of using a high-thermal-conductivity material (non-SiO2) in the isolation region is identical across all claims. "VHDC" and "Heat Removing Layer" are obvious functional equivalents naming the same physical feature.
Geometry & Location
VHDC surrounds the semiconductor body region.
Heat removing layer is close to the source/drain of the transistor.
Heat removing layer extends
along the active regions.
Heat removing layer is within the STI neighboring the active regions.
"Surrounding" a region (as in '720) is a geometric genus or obvious variation of "neighboring" or "extending along" (as in '888/'649). Placing isolation/heat structures around active areas is standard STI topology.
Extension/ Routing
(General heat dissipation described).
Extends to a spare STI region remote from active regions.
Extends to a spare STI region
remote from active regions.
Extends to a (spare) STI region.
The references claim a specific species of routing (to a "spare" region). If Claim 1 of '720 is broader (generic heat column without specifying the "spare" destination), it is anticipated by the specific disclosure of the references. A generic claim is ODP over a specific claim.
All four applications claim a semiconductor structure where the standard Shallow Trench Isolation (STI) is modified to include a material (e.g., AlN, BN, or metal) with thermal conductivity higher than Silicon Oxide (SiO2) to facilitate direct heat removal from the active device (transistor).
The term "Vertical Heat Dissipation Column" (VHDC) in 18/533720 describes the vertical profile of the filled trench. This is structurally indistinguishable from the "Heat Removing Layer" recited in 18/980888, 18/674649, and 19/308894 which fills the STI trench.
Application 18/533720 appears to claim the broad concept of the vertical heat structure surrounding the device.
Applications 18/980888, 18/674649, and 19/308894 claim specific implementations involving "spare STI regions," "thermal vias," or specific routing geometries.
It is known that a generic claim (broad heat column) is indistinct from a specific claim (heat column extending to a spare region) because the specific embodiment necessarily includes the generic features. Therefore, 18/533720 is obvious in light of the specific embodiments claimed in the co-pending applications.
Therefore, claim 1 of US 18/533,720 is patentably indistinct from the claims of US 18/980,888, US 18/674,649, and US 19/308,894.
Claim 16 is rejected on the ground of non-statutory double patenting as being unpatentable over Claims 1, 11, 13, and 14 of co-pending Application No. 18/980,888.
Although the claims at issue are not identical, they are not patentably distinct from each other.
Limitation from Claim 16 (US 18/533,720)
Corresponding Limitation from US 18/980,888
Claim No.
A device structure, comprising:
A semiconductor circuit structure comprising:
1
a semiconductor substrate with an original semiconductor surface
a semiconductor substrate with an original semiconductor surface
1
a first transistor located within a first semiconductor body region of the semiconductor substrate
a transistor is located within a first active region of the set of active regions, the transistor comprises a gate structure, a source region, and a drain region
1
a second transistor located within a second semiconductor body region of the semiconductor substrate, wherein the second transistor is remote from, rather than next to, the first transistor
the spare STI region is remote from the set of active regions (implying multiple active regions with transistors, where the spare region is remote from the transistor locations)
1, 11
a vertical heat dissipation column in the semiconductor substrate
the first STI region includes a heat removing layer
1
wherein the vertical heat dissipation column comprises a thermal dissipation material with a thermal conductivity higher than that of the semiconductor substrate or that of silicon oxide
the thermal conductivity of the heat removing layer is higher than that of SiO₂
1
wherein the vertical heat dissipation column extends from the first semiconductor body region to the second semiconductor body region
the heat removing layer extends along the first direction to the spare STI region; the spare STI region is connected to the first STI region, and the heat removing layer extends along the first direction to the spare STI region
1, 11
The claims are not identical but are not patentably distinct for the following reasons:
The "vertical heat dissipation column" of US 18/533720 corresponds to the "heat removing layer" within the STI region of US 18/980888. Both specifications describe these structures as being formed within STI regions using high thermal conductivity materials (referred to as "Z material" in both specifications), including BN, AlN, tungsten, or composite materials.
Both claim sets are directed to enhancing heat dissipation from transistor regions by replacing or supplementing conventional SiO₂ STI material with higher thermal conductivity materials.
Claim 16 of US 18/533720 requires the vertical heat dissipation column to extend "from the first semiconductor body region to the second semiconductor body region." US 18/980888 Claim 1 requires the heat removing layer to extend "along a first direction to a spare STI region" where the spare STI region is "remote from the set of active regions." The specifications of both applications describe how the heat dissipation structures (VHDC) extend between and among multiple active regions across the die (see, e.g., FIG. 10) of both applications, which show interconnected heat dissipation networks spanning multiple active regions).
To the extent that Claim 16 of US 18/533720 explicitly requires a "second transistor" in a second body region while US 18/980888 Claim 1 recites "a set of active regions" with transistors, it would have been obvious to one of ordinary skill in the art that a semiconductor circuit structure inherently includes multiple transistors in multiple active regions, and that heat dissipation structures extending across the die would necessarily extend between regions containing transistors. The specification of US 18/980888 explicitly describes VHDC structures extending from one active region to another active region, and FIG. 14a shows multiple active areas 220A with VHDC structures 205 extending between them.
Claim 16 of US Application No. 18/533,720 is not patentably distinct from Claims 1, 11, and 13 (and optionally 14) of co-pending Application No. 18/980,888. The differences in claim terminology ("vertical heat dissipation column" vs. "heat removing layer within STI region") do not distinguish the claimed inventions because both refer to the same structural feature as disclosed in the commonly shared specification content. The requirement in Claim 16 of '720 for the heat dissipation column to extend between two transistor body regions is an obvious variation of the heat removing layer extending between active regions and to spare STI regions as claimed in '888.
Claim 16-23 are rejected on the ground of non-statutory double patenting as being unpatentable over Claims 1, 9-11, 13-19 co-pending Application No. 19/308894.
Although the claims at issue are not identical, they are not patentably distinct from each other because:
Claim 16 (US 18/533,720)
US 19/308,894
A semiconductor substrate with an original semiconductor surface
Claim 1: "a semiconductor substrate with an original semiconductor surface"
A first transistor located within a first semiconductor body region of the semiconductor substrate
Claim 1: "a transistor is located within a first active region of the set of active region"
A second transistor located within a second semiconductor body region, wherein the second transistor is remote from, rather than next to, the first transistor
Claim 11: "the first STI region extends along a first direction to a spare STI region, the spare STI region is remote from the set of active regions" (implies multiple active regions with transistors that are remote from each other)
A vertical heat dissipation column in the semiconductor substrate
Claim 1: "the first STI region includes a heat removing layer" / Claims 13-14: "heat removing pad" and "thermal via"
Wherein the vertical heat dissipation column comprises a thermal dissipation material with a thermal conductivity higher than that of the semiconductor substrate or that of silicon oxide
Claim 1: "the thermal conductivity of the heat removing layer is higher than that of SiO₂"
Wherein the vertical heat dissipation column extends from the first semiconductor body region to the second semiconductor body region
Claim 11: "the heat removing layer extends along the first direction to the spare STI region" (extending between active regions)
Both applications claim semiconductor device structures with:
A semiconductor substrate having an original semiconductor surface
Transistors formed within active regions of the semiconductor substrate
Heat dissipation structures (called "vertical heat dissipation column" in '720 and "heat removing layer/pad" in '894) comprising materials with thermal conductivity higher than silicon oxide
The heat dissipation structures extend between semiconductor body regions/active regions
The primary difference is one of terminology and claim scope: US 18/533,720 claims a "vertical heat dissipation column" extending between first and second transistor body regions.
US 19/308,894 claims a "heat removing layer" in an STI region that extends to and surrounds active regions containing transistors
Claim 1 of US 19/308,894 additionally requires the transistor to be a FinFET or GAA transistor, which is a species of the genus claimed in US 18/533,720. One of ordinary skill would recognize that the "heat removing layer" in the STI region of '894 that extends along and surrounds active regions performs the same function as the "vertical heat dissipation column" of '720 that extends between semiconductor body regions.
It would have been obvious to one of ordinary skill in the art that the claimed structures are essentially the same heat dissipation architecture within semiconductor devices, differing only in claim drafting terminology and minor structural variations that do not distinguish patentably over one another.
Claims 2-15 depend from independent claim 1. Although these dependent claims have not been separately compared with corresponding claims of the co-pending application(s), they are nonetheless rejected by virtue of their dependency on the rejected base claim 1.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893