Prosecution Insights
Last updated: August 16, 2026
Application No. 18/533,721

SEMICONDUCTOR DEVICE

Final Rejection §103
Filed
Dec 08, 2023
Priority
Jul 06, 2021 — JP 2021-112383 +1 more
Examiner
PARK, SAMUEL
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co., Ltd.
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
405 granted / 479 resolved
+16.6% vs TC avg
Strong +24% interview lift
Without
With
+23.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
32 currently pending
Career history
508
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
54.0%
+14.0% vs TC avg
§102
23.2%
-16.8% vs TC avg
§112
21.0%
-19.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 479 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicant’s amendment to the claims, filed on June 12, 2026, is acknowledged. Entry of amendment is accepted and made of record. Response to Arguments/Remarks Applicant’s arguments/remarks, see pgs. 5-8, with respect to the immediate allowance of the current application have been fully considered but are not persuasive. Pertaining to the Applicant’s arguments/remarks, pgs. 5-8, regarding the newly amended limitations in claim 1: The Examiner notes that the manner in which the claim is currently recited requires “in a planar view, an entirety of the coating member is disposed in an area surrounded by the bonding sections of the plurality of first wires” which does not sufficiently limit the claim such as to distinguish from the outstanding rejection as opposed to if the claim were to recite “in a planar view, the coating member is entirely surrounded by the bonding sections of the plurality of first wires”. As currently amended the claim requires the entirety of the coating member to be disposed in an area which is disclosed by Kaji, the area occupied by coating member element 11, and for the area to be surrounded by the bonding sections of the plurality of first wires which is disclosed by the combination of Kaji and Eldridge – note, the combination discloses surrounded on two sides. Note from the Examiner For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 and 103 rejections have been provided in parenthesis. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3 and 10-11 are rejected under 35 U.S.C. 103 as obvious over Kaji et al. (WO 2020136810 A1), hereinafter referred to as “Kaji” (please note that all citations from Kaji herein are made with reference to the Espacenet English translation of Kaji received from applicant on December 8, 2023), in view of Eldridge et al. (US20010020545 A1), hereinafter referred to as “Eldridge”. [Matsuoka et al. (US 20100002455 A1), hereinafter referred to as “Matsuoka”. Is utilized herein as evidence]. Regarding Claim 1, Kaji discloses a semiconductor device (fig. 2, 100) comprising: a semiconductor element (fig. 2, 5; see [0017]) including a first electrode (fig. 2, 51; see [0017]); a sealing resin (fig. 2, 4; see [0026] and note that filling member 4 is made of silicone resin) covering the semiconductor element (see fig. 2: filling member 4 completely covers semiconductor element 5); and a coating member (fig. 2, 11; see [0027]-[0028]), wherein the coating member is interposed between the first electrode and the sealing resin (see fig. 2: metal thin film member 11 is disposed between electrode 51 and filling member 4), and contains a material (the metal thin film member 11 contains silver; see [0028]: “[a]s the material of the metal thin film member 11 … gold, silver, titanium, copper, nickel or the like can be used”) with higher thermal conductivity than the sealing resin (the silver (Ag) material of the metal thin film member 11 has a higher thermal conductivity than the silicone resin material of filling member 4; see evidentiary reference Matsuoka [0004]: “such as epoxy resin or silicone resin, which has a low thermal conductivity of 1.0 W/mK or less”; also see evidentiary reference Matsuoka [0155]: “Cu (having a thermal conductivity of 403 W/mK), Ni (having a thermal conductivity of 94 W/mK), Au (having a thermal conductivity of 319 W/mK), Ag (having a thermal conductivity of 428 W/mK), Pd (having a thermal conductivity of 72 W/mK), Sn (having a thermal conductivity of 68 W/mK), or Al (having a thermal conductivity of 236 W/mK)”), Kaji does not discloses a plurality of first wires including respective bonding sections joined to the first electrode; the bonding sections of the plurality of first wires are disposed along an outer edge of the first electrode, and in a planar view, an entirety of the coating member is disposed in an area surrounded by the bonding sections of the plurality of first wires. Eldridge discloses techniques for interconnecting microelectronic components (see Eldridge [0048]) and making wire bond connections (See Eldridge [0052]; also see Eldridge [0003] and note that it is well known in the art to make wire bond connections between conductive pads (i.e. electrodes) on semiconductor dies). Eldridge further discloses one such wire bond connection (see Eldridge fig. 5 and [0455]) in which a wire (Eldridge fig. 5, 502; see Eldridge [0460]) that includes a bonding section (Eldridge fig. 5, 502a; see Eldridge [0460]) is connected to an electrode (Eldridge fig. 5, 512; see Eldridge [0460]), wherein both the bonding section and the electrode are covered by a conductive coating member (Eldridge fig. 5, 520; see Eldridge [0460] and [0463]-[0466]). The bonding section of Eldridge is incorporated with the first wires of Kaji connecting said first wires to the first electrode of Kaji (Kaji fig. 2, 51; see specifically the leftmost semiconductor element 5 in Kaji fig. 2) and wherein the combination discloses, PNG media_image1.png 365 820 media_image1.png Greyscale PNG media_image2.png 614 805 media_image2.png Greyscale a plurality of first wires (Kaji fig. 2, 6) including respective bonding sections (Eldridge fig. 5, 502a combined with Kaji) joined to the first electrode (Kaji fig. 2, 51); the bonding sections of the plurality of first wires are disposed along an outer edge of the first electrode (Kaji fig. 2, 6), and in a planar view, an entirety of the coating member is disposed in an area surrounded by the bonding sections of the plurality of first wires (surrounded on two sides; note, the manner in which the claim is currently recited does not require the coating member to be entirely surrounded by the bonding sections of the plurality of first wires) Regarding claim 2, Kaji and Eldridge disclose the semiconductor device according to claim 1, wherein (see Kaji) the coating member (fig. 2, 11; see [0028]: metal thin film member 11 contains silver (Ag)) contains a metal. Regarding claim 3, Kaji and Eldridge disclose the semiconductor device according to claim 2, wherein (see Kaji) the coating member (fig. 2, 11; see [0028]: metal thin film member 11 contains silver (Ag)) contains Ag or Cu. Regarding claim 10, Kaji and Eldridge disclose the semiconductor device according to claim 1, wherein each first wire (Kaji fig. 2, 6; see Kaji [0025]: bonding wire 6 is made of a copper alloy) contains Cu. Regarding claim 11, Kaji and Eldridge disclose the semiconductor device according to claim 1, wherein the coating member (Kaji fig. 2, 11; see Kaji [0027]-[0028]) is in contact with the bonding section (Eldridge fig. 5, 502a) of each first wire (Kaji fig. 2, 6; see Kaji [0027]: metal thin film member 11 electrically connects bonding wires 6 and electrode 51 through direct contact; since, in the combined device, the bonding sections electrically connect each bonding wire 6 to electrode 51, the bonding sections are also electrically connected and in direct contact with metal thin film member 11 disposed thereon). Claim 4 is rejected under 35 U.S.C. 103 as obvious over Kaji, in view of Eldridge, in view of Kajiwara et al. (US 20140264383 A1), hereinafter referred to as “Kajiwara”. Regarding claim 4, Kaji and Eldridge disclose the semiconductor device according to claim 3. Kaji and Eldridge fails to disclose wherein the coating member contains sintered Ag or sintered Cu. Kajiwara discloses a semiconductor device (Kajiwara fig. 16, 35) comprising a semiconductor element (Kajiwara fig. 16, 1; see Kajiwara [0053]; also see Kajiwara [0177]: SiC chip 1 is the same in the second embodiment of fig. 16 as in the first embodiment of fig. 2) with a coating member (Kajiwara fig. 16, 36; see Kajiwara [0184]-[0185]: note that the silver (Ag) layer 36 is sintered) interposed between a first electrode (Kajiwara fig. 16, 2; see Kajiwara [0181]) and a sealing resin body (Kajiwara fig. 16, 14; see Kajiwara [0071]-[0072]; also see Kajiwara [0177]: sealing body 14 is the same in the second embodiment of fig, 16 as in the first embodiment of fig. 2). The coating member of Kajiwara is incorporated as a portion of the coating member of the device taught in Kaji between the first electrode and the sealing resin wherein the combination discloses wherein the coating member contains sintered Ag or sintered Cu. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kaji with the coating member of Kajiwara to uniformly disperse incoming current across the first electrode and thereby suppress the occurrence of local overheating (see Kajiwara [0188]-[0189]); and the combination is a simple substitution of one known element for another to obtain predictable results—simple substitution of a portion of the coating member of Kaji (Kaji fig. 2, 51: the portion between electrode 51 and sealing resin 4) with the coating member of Kajiwara (Kajiwara fig. 16, 36) to obtain predictable results (i.e. suppression of local overheating). Claims 5, 9, 12-16, and 18 are rejected under 35 U.S.C. 103 as obvious over Kaji, in view of Eldridge, further in view of Okuda. Regarding Claim 5, Kaji and Eldridge disclose the semiconductor device according to claim 1. Kaji and Eldridge fail to disclose wherein the first electrode contains Al. Okuda discloses a semiconductor device (Okuda fig. 2, A10; see [0045]) comprising a semiconductor element (Okuda fig. 2, 11; see Okuda [0046]) including a first electrode (Okuda fig. 2, 111a; see Okuda [0047]: “second electrode 111a and the third electrode 111b are composed of a Cu layer and an Al layer mutually laminated”; note that second electrode 111a contains aluminum (Al)), wherein sealing resin (Okuda fig. 2, 6; c.f. the cross-sectional view of Okuda fig. 4; see Okuda [0044]; note that sealing resin 6 covers semiconductor element 11) covers the semiconductor element. The first electrode of Okuda is incorporated as the first electrode of Kaji wherein the combination discloses wherein the first electrode contains Al. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kaji with the first electrode of Okuda because of the affordability of aluminum compared to other suitable electrode metals; and the combination is a simple substitution of one known element for another to obtain predictable results—simple substitution of the first electrode of Kaji with (Kaji fig. 2, 51) with the first electrode of Okuda (Okuda fig. 2, 111a) to obtain predictable results (the result would be predictable because one of ordinary skill in the art would recognize that the aluminum first electrode of Okuda would perform the same function as the first electrode of Kaji (i.e. conducting electrical current)). Regarding claim 9, Kaji and Eldridge disclose the semiconductor device according to claim 1. Kaji and Eldridge fail to explicitly disclose wherein each first wire contains a metal different from a metal contained in the first electrode. Okuda discloses a semiconductor device (Okuda fig. 2, A10; see [0045]) comprising a semiconductor element (Okuda fig. 2, 11; see Okuda [0046]) including a first electrode (Okuda fig. 2, 111a; see Okuda [0047]: “second electrode 111a and the third electrode 111b are composed of a Cu layer and an Al layer mutually laminated”; note that second electrode 111a contains aluminum (Al)), wherein sealing resin (Okuda fig. 2, 6; c.f. the cross-sectional view of Okuda fig. 4; see Okuda [0044]; note that sealing resin 6 covers semiconductor element 11) covers the semiconductor element. The first electrode of Okuda is incorporated as the first electrode of the combined device of Kaji and Eldridge wherein the combination discloses wherein each first wire (Kaji fig. 2, 6; see Kaji [0025]: bonding wire 6 is made of a copper alloy) contains a metal different from a metal contained in the first electrode (the first electrode of Okuda contains aluminum and the bonding wires of Kaji contain copper). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Kaji and Eldridge with the first electrode of Okuda because of the affordability of aluminum compared to other suitable electrode metals; and the combination is a simple substitution of one known element for another to obtain predictable results—simple substitution of the first electrode of Kaji with (Kaji fig. 2, 51) with the first electrode of Okuda (Okuda fig. 2, 111a) to obtain predictable results (the result would be predictable because one of ordinary skill in the art would recognize that the aluminum first electrode of Okuda would perform the same function as the first electrode of Kaji (i.e. conducting electrical current)). Regarding claim 12, Kaji and Eldridge disclose the semiconductor device according to claim 1. Kaji and Eldridge do not disclose further comprising at least one metal lump joined to the first electrode. Okuda discloses a semiconductor device (Okuda fig. 2, A10; see [0045]) comprising a semiconductor element (Okuda fig. 2, 11; see Okuda [0046]) including a first electrode (Okuda fig. 2, 111a; see Okuda [0047]: “second electrode 111a and the third electrode 111b are composed of a Cu layer and an Al layer mutually laminated”; note that second electrode 111a contains aluminum (Al)), wherein sealing resin (Okuda fig. 2, 6; c.f. the cross-sectional view of Okuda fig. 4; see Okuda [0044]; note that sealing resin 6 covers semiconductor element 11) covers the semiconductor element and wherein a plurality of metal lumps (Okuda fig. 6, 4; see Okuda [0062] and c.f. fig. 7; also see Okuda [0019]-[0020]: figs. 6-7 show close-up views of the semiconductor device 11 shown in fig. 2) and wires (Okuda fig. 6, 31; see Okuda [0060]) with bonding sections (Okuda fig. 7, 311; c.f. Okuda fig. 6) are joined to the first electrode. The metal lumps of Okuda are incorporated into the combined device of Kaji, Eldridge, and Okuda, wherein the metal lumps are connected to the first electrode and disposed in an area surrounded by the first wires. Therefore, the combination discloses wherein further comprising at least one metal lump joined to the first electrode. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Kaji, Eldridge, and Okuda, with the metal lumps of Okuda to uniformly and efficiently release heat from the electrode (see Okuda [0073]). Regarding claim 13, Kaji, Eldridge, and Okuda disclose the semiconductor device according to claim 12, wherein the metal lump (Okuda fig. 6, 4; see Okuda [0062] and c.f. fig. 7) contains a metal different from a metal contained in the first electrode (see Okuda [0062]: heat releasing member 4 is composed of Copper (Cu); the first electrode of the combined device contains aluminum (Al)). Regarding claim 14, Kaji, Eldridge, and Okuda disclose the semiconductor device according to claim 12, wherein the coating member (Kaji fig. 2, 11; see Kaji [0027]-[0028]) is in contact with the metal lump (Okuda fig. 6, 4; see Okuda [0062] and c.f. fig. 7; see Kaji [0027]: metal thin film member 11 electrically connects bonding wires 6 and electrode 51 through direct contact; since, in the combined device, the metal lumps of Okuda contact the first electrode, said coating member is in contact with said metal lump). Regarding claim 15, Kaji, Eldridge, and Okuda disclose the semiconductor device according to claim 14, wherein the coating member (Kaji fig. 2, 11; see Kaji [0027]-[0028]) covers the metal lump (Okuda fig. 6, 4; see Eldridge fig. 5 and note that proximal end 502a is covered by inner coating layer 520; see Okuda fig. 7 and note that heat releasing members 4 are approximately the same size as bonding portions 311; thus, in the combined device, said coating member covers both said metal lump and the bonding sections associated with each of the first wires). Regarding claim 16, Kaji, Eldridge, and Okuda disclose the semiconductor device according to claim 15, wherein a maximum thickness of the coating member (Kaji fig. 2, 11; see Kaji [0027]-[0028]) is greater than a thickness of the bonding section (Eldridge fig. 5, 502a) of each first wire (Kaji fig. 2, 6; see Eldridge fig. 5 and note that a maximum thickness of inner coating layer 520 is greater than a thickness of proximal end 502a; thus, in the combined device, the maximum thickness of said coating member is greater than the thickness of said bonding section of each first wire). Regarding claim 18, Kaji, Eldridge, and Okuda disclose the semiconductor device according to claim 15, wherein the maximum thickness of the coating member (Kaji fig. 2, 11; see Kaji [0028]: “the thickness of the metal thin film member 11 is preferably 0.1 μm or more and 50 μm or less”) is at least 20 μm (see MPEP 2144.05 I. "In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)"). Claims 17 and 19-20 are rejected under 35 U.S.C. 103 as obvious over Kaji, in view of Eldridge further in view of Okuda, further in view of Kajiwara. Regarding claim 17, the combined device of Kaji, Eldridge, and Okuda, disclose the semiconductor device according to claim 15. The combined device of Kaji, Eldridge, and Okuda, fail to explicitly disclose wherein the coating member includes a periphery and a center portion that is thicker than the periphery. Kajiwara discloses a semiconductor device (Kajiwara fig. 16, 35) comprising a semiconductor element (Kajiwara fig. 16, 1; see Kajiwara [0053]; also see Kajiwara [0177]: SiC chip 1 is the same in the second embodiment of fig. 16 as in the first embodiment of fig. 2) with a coating member (Kajiwara fig. 16, 36; see Kajiwara [0184]-[0185]) interposed between a first electrode (Kajiwara fig. 16, 2; see Kajiwara [0181]) and a sealing resin body (Kajiwara fig. 16, 14; see Kajiwara [0071]-[0072]; also see Kajiwara [0177]: sealing body 14 is the same in the second embodiment of fig. 16 as in the first embodiment of fig. 2). The coating member of Kajiwara is incorporated as a portion of the coating member of the combined device of Kaji, Eldridge, and Okuda, between the first electrode and the sealing resin wherein the combination discloses wherein the coating member includes a periphery and a center portion that is thicker than the periphery (see Kajiwara fig. 16: a central portion of sintered Ag layer 36 is thicker than a peripheral portion of said layer as shown). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Kaji, Eldridge, and Okuda, with the coating member of Kajiwara to uniformly disperse incoming current across the first electrode and thereby suppress the occurrence of local overheating (see Kajiwara [0188]-[0189]); and the combination is a simple substitution of one known element for another to obtain predictable results—simple substitution of a portion of the coating member of the combined device of Kaji, Eldridge, and Okuda (Kaji fig. 2, 11: the portion between electrode 51 and sealing resin 4), with the coating member of Kajiwara (Kajiwara fig. 16, 36) to obtain predictable results (i.e. suppression of local overheating). Regarding claim 19, Kaji, Eldridge, Okuda, and Kajiwara disclose the semiconductor device according to claim 15, wherein the maximum thickness of the coating member (Kajiwara fig. 16, 36; see Kajiwara [0184]: “a porous second sintered Ag layer 36 having a thickness of 30 μm or more) is at least 80 μm (see MPEP 2144.05 I. "In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)"). Regarding claim 20, Kaji, Eldridge, Okuda, and Kajiwara disclose the semiconductor device according to claim 15, wherein the maximum thickness of the coating member (Kajiwara fig. 16, 36; see Kajiwara [0184]: “a porous second sintered Ag layer 36 having a thickness of 30 μm or more) is at least 160 μm (see MPEP 2144.05 I. "In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)"). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAMUEL PARK/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Dec 08, 2023
Application Filed
Mar 18, 2026
Non-Final Rejection mailed — §103
Jun 12, 2026
Response Filed
Aug 05, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707963
Semiconductor Devices Including Backside Capacitors and Methods of Manufacture
4y 5m to grant Granted Aug 11, 2026
Patent 12696448
SEMICONDUCTOR DEVICE
4y 1m to grant Granted Jul 28, 2026
Patent 12685236
Semiconductor Device Packages and Methods of Forming the Same
3y 11m to grant Granted Jul 14, 2026
Patent 12684940
DISPLAY PANEL
2y 10m to grant Granted Jul 14, 2026
Patent 12677695
LIGHT-EMITTING DEVICES WITH REINFORCEMENT MATERIALS AND RELATED METHODS
4y 5m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+23.7%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 479 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month