Prosecution Insights
Last updated: May 29, 2026
Application No. 18/533,809

POWER MODULE AND METHOD FOR PRODUCING A POWER MODULE

Non-Final OA §103
Filed
Dec 08, 2023
Priority
Dec 14, 2022 — DE 10 2022 213 634.9
Examiner
CHOUDHRY, MOHAMMAD M
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Robert Bosch GmbH
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
563 granted / 690 resolved
+13.6% vs TC avg
Moderate +12% lift
Without
With
+12.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
25 currently pending
Career history
729
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
93.3%
+53.3% vs TC avg
§102
1.7%
-38.3% vs TC avg
§112
1.0%
-39.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 690 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions In response to Election/Restrictions, applicant elected claims 16-26. Election was made without traverse in the reply filed on 04/27//2026. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 16-22, and 24-35 are rejected under 35 U.S.C. 103 as being unpatentable over Cottet et al. (US 2017/0338162, hereinafter Cottet) in view of Bayerer (US 9,355,950, hereinafter Bayerer). With respect to claim 16, Cottet discloses a power module (Fig. 1), comprising: a first circuit carrier (12 of Fig. 1 – Para 0010, DBC (direct bond copper) substrate), on an upper side of which at least one first conductor structure (Para 0014- two intermediate metallization areas), having two internal contact regions (Para 0014-0015) which are arranged mirror-symmetrically to a central longitudinal axis (Para 0022, 0034, 0063 and 0073; mirror symmetric to a symmetry axis of the inner metallization area) and on each of which a first power terminal of at least one first semiconductor switch (para 0010; 0016; 0022; 0035-0036; switches and terminals are contacted), is arranged and contacted (Para 0010), and at least one second conductor structure having two internal contact regions (Para 0014 - two outer metallization areas) which are arranged mirror-symmetrically to the central longitudinal axis and on each of which a first power terminal of at least one second semiconductor switch is arranged and contacted (para 0010; 0016; 0022; 0035-0036; switches and terminals are contacted), are formed (Para 0016, 0022, and 0032- outer sets of switches bonded to outer areas), wherein second power terminals of the first semiconductor switches are each contacted with a common third internal contact region of the at least one second conductor structure, which third internal contact region is arranged between the first internal contact region and the second internal contact region of the at least one first conductor structure (Para 0022, 0025-0028 – inner metallization area serves as the shared contact- switches connect electrically to the inner metallization layer), wherein second power terminals of the second semiconductor switches are each contacted with a common internal contact region of at least one third conductor structure, which common internal contact region is arranged between the first internal contact region and the second internal contact region of the at least one second conductor structure (Para 0022, 0025-0028 – inner metallization area serves as the shared contact- switches connect electrically to the inner metallization layer). Cottet does not explicitly disclose that the first circuit carrier has an electrically insulating layer; and at least two further circuit carriers arranged spatially in parallel above the first circuit carrier, and each have at least one internal contact region, at which control terminals of the first and second semiconductor switches are contacted, and each have at least one external contact region which can be electrically connected to an external control circuit, and wherein each of the at least two further circuit carriers is a strip-shaped flexible printed circuit board arranged at opposite edges of the first circuit carrier. In an analogous art, Bayerer discloses that the first circuit carrier has an electrically insulating layer (Col.3; lines 50-67); and at least two further circuit carriers arranged spatially in parallel above the first circuit carrier (Col. 4; lines 30-60 – 106 & 108 are arranged parallel to power board/ DCB), and each have at least one internal contact region, at which control terminals of the first and second semiconductor switches are contacted (Col. 4; lines 13-25; Col. 6; lines 5-20), and each have at least one external contact region which can be electrically connected to an external control circuit (Col. 9; lines 45-50 – the flexible board can protrude out of the module housing and make contact to a driver circuit external to the module housing), and wherein each of the at least two further circuit carriers is a strip-shaped flexible printed circuit board arranged at opposite edges of the first circuit carrier (Col. 4; lines 14-25 – Fig. 12 – parts of 106 and 108 can be on opposite edges). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Cottet’s method/system by having Bayerer’s disclosure in order to improve turn on and off responses of power devices. With respect to claim 17, Cottet discloses wherein the at least one first conductor structure can be contacted via at least one external contact region with a first supply terminal (Para 0014 - the outer metallization areas), and the at least one second conductor structure can be contacted via at least one external contact region with a load terminal (Para 0014- intermediate metallization areas), and the at least one third conductor structure can be contacted via at least one external contact region with a second supply terminal (inner metallization area). With respect to claim 18, Cottet discloses wherein the at least one first semiconductor switch, which is arranged on the second internal contact region of the at least one first conductor structure, is oriented SO as to be rotated by 180° relative to the at least one first semiconductor switch, which is arranged on the opposite first internal contact region of the at least one first conductor structure (Para 0022, 0025, and 0027 – the intermediate metallization areas are arranged mirror-symmetrically to the inner metallization area). With respect to claim 19, Cottet discloses wherein the at least one second semiconductor switch, which is arranged on the second internal contact region of the at least one second conductor structure, is oriented so as to be rotated by 180° relative to the at least one second semiconductor switch, which is arranged on an opposite first internal contact region of the at least one second conductor structure (Para 0022, 0025, and 0027 – two internal contact regions of the outer conductor structure are arranged mirror symmetrically to the inner metallization area). With respect to claim 20, Cottet discloses wherein the second power terminals of the first semiconductor switches are each contacted via at least one power connection with the third internal contact region of the at least one second conductor structure (Para 0016 – inner set of semiconductor switches are bonded to the intermediate area), and the second power terminals of the second semiconductor switches are each contacted via at least one power connection with the internal contact region of the at least one third conductor structure (Para 0038-0039 - terminals bonded to the inner metallization area) With respect to claim 21, Cottet discloses wherein the control terminals of the at least one first semiconductor switch, which is arranged on the first internal contact region of the at least one first conductor structure (Para 0032), and the control terminals of the at least one second semiconductor switch (Para 0023), which is arranged on the first internal contact region of the at least one second conductor structure (Para 0026), are each contacted via signal connections with a common internal contact region of a first further circuit carrier (Para 0031-0034). With respect to claim 22, Cottet discloses wherein the control terminals of the at least one first semiconductor switch, which is arranged on the second internal contact region of the at least one first conductor structure (Para 0014-0015), and the control terminals of the at least one second semiconductor switch (Para 0016), which is arranged on the second internal contact region of the at least one second conductor structure, are each contacted via signal connections with a common internal contact region of a second further circuit carrier (Para 0031, 0034). With respect to claim 24, Cottet does not explicitly disclose wherein a first external contact region of a first further circuit carrier is configured to be electrically contacted with a first external contact device that has a contact region with multiple contact elements which can be connected to the contact elements of the first external contact devices (Para 0014; 0034-0035). Cottet does not explicitly disclose that the connections are soldered connections or welded connections or adhesive connections or plug connections. In an analogous art, Bayerer discloses that the connections are soldered connections or welded connections or adhesive connections or plug connections (Col. 5, lines 38-41). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Cottet’s method/system by having Bayerer’s disclosure in order to improve turn on and off responses of power devices. With respect to claim 25, Cottet does not explicitly disclose wherein a second external contact region of a second further circuit carrier is configured to be electrically contacted with a second external contact device that has a contact region with multiple contact elements which can be connected to contact elements of the second external contact device (Para 0014; 0034-0035). Cottet does not explicitly disclose that the connections are soldered connections or welded connections or adhesive connections or plug connections. In an analogous art, Bayerer discloses that the connections are soldered connections or welded connections or adhesive connections or plug connections (Col. 5, lines 38-41). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Cottet’s method/system by having Bayerer’s disclosure in order to improve turn on and off responses of power devices. With respect to claim 26, Cottet discloses wherein the power module is overmolded by an enclosure (71 of Fig. 8), the enclosure having a cut-out in each case in a region of the first and second external contact regions of the first circuit carrier so that the at least one external contact region of the first circuit carrier can be contacted (Fig. 8 – there are cuts in 71 to make external contacts), and an exposure being made in each case in the enclosure in regions of the at least one external contact region of the at least two further circuit carriers so that contact elements of the at least one external contact region of the at least two further circuit carriers are exposed and contactable (Para 0004, 0040, 0079 and 0111). With respect to claim 31, Cottet discloses wherein the power module is overmolded by an enclosure (71 of Fig. 8), wherein the enclosure includes one or more cut-outs in regions of external contact regions of the first circuit carrier so that the external contact regions of the first circuit carrier are exposed and contactable (Fig. 8 – there are cuts in 71 to make external connections), and wherein the enclosure includes, in regions of the at least one external contact region of each of the at least two further circuit carriers (Para 0023-0025), a respective exposure through which contact elements of the at least one external contact region of the respective further circuit carrier are exposed and contactable (Para 0004, 0031 and 0040). With respect to claim 32, Cottet discloses wherein the power module is overmolded by an enclosure (71 of Fig. 8) that includes respective exposures in regions of the at least one external contact region of the at least two further circuit carriers SO that contact elements of the at least one external contact region of the at least two further circuit carriers are exposed and contactable (Para 0045, 0079 – housing). With respect to claim 33, Cottet discloses wherein a layout of the first circuit carrier as a whole is mirror-symmetrical to the central longitudinal axis (Para 0018, 0022, 0063, 0066). With respect to claim 34, Cottet does not explicitly disclose wherein the at least two further circuit carriers are connected to the first circuit carrier via soldered connections, welded connections, adhesive connections, or sintered connections. In an analogous art, Bayerer discloses wherein the at least two further circuit carriers are connected to the first circuit carrier via soldered connections, welded connections, adhesive connections, or sintered connections (Col. 5, lines 38-41). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Cottet’s method/system by having Bayerer’s disclosure in order to improve turn on and off responses of power devices. With respect to claim 35, Cottet does not explicitly disclose wherein the connection of the at least two further circuit carriers to the first circuit carrier is at the opposite edges of the first circuit carrier. In an analogous art, Bayerer discloses wherein the connection of the at least two further circuit carriers to the first circuit carrier is at the opposite edges of the first circuit carrier. (Col. 4; lines 14-25 – Fig. 12 – parts of 106 and 108 can be on opposite edges). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Cottet’s method/system by having Bayerer’s disclosure in order to improve turn on and off responses of power devices. Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Cottet/Bayerer in view of Schober et al. (US 2019/0080945, hereinafter Schober). With respect to claim 23, Cottet/Bayerer does not explicitly disclose wherein layouts of the at least two further circuit carriers are identical, and the at least two further circuit carriers are arranged so as to be rotated by 180° relative to one another about a vertical axis. In an analogous art, Schober discloses wherein layouts of the at least two further circuit carriers are identical (Para 0047 and 0175 – identical substrate carriers), and the at least two further circuit carriers are arranged so as to be rotated by 180° relative to one another about a vertical axis (Para 0055 and 0057- two substrate carriers rotated about a vertical rotation axis by 180). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Cottet/Bayerer’s method/system by having Schober’s disclosure in order to provide proper relative positioning of the substrate carriers to improve the processing and minimizing the size of the device. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fairbanks Brent can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Dec 08, 2023
Application Filed
May 20, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
94%
With Interview (+12.2%)
2y 9m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 690 resolved cases by this examiner. Grant probability derived from career allowance rate.

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