DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation “the portion of the upper surface of the protrusion pattern exposed by the bonding pad”. There is insufficient antecedent basis for this limitation. Neither claim 13 or claim 11, on which claim 13 depends, do not disclose the bonding pad exposing a portion of the upper surface of the protrusion pattern. For the purpose of examination, claim 13 will be interpreted as: The semiconductor package of Claim 12, wherein the electrically conductive bump completely covers a portion of the upper surface of the protrusion pattern exposed by the bonding pad.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 6, 8-12 and 16-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by disclosed prior art, Kim et al., (United States Patent Application Publication Number, US 2022/0352059 A1), hereinafter referenced as Kim_059.
Regarding claim 1, Kim_059 teaches a semiconductor package, comprising: a semiconductor chip (Fig.2, element #110) having chip pads extending adjacent a first surface thereof (Fig.2, elements #111, adjacent to the top surface of element #110); a redistribution wiring layer covering at least a portion of the first surface of the semiconductor chip (Fig.2, element #130), said redistribution wiring layer including: redistribution wirings with redistribution patterns provided on a first insulating layer (Fig.2, parts of element #141 are provided on top of element #131a, paragraph [0107], rows 1-2) and electrically connected to the chip pads (Fig.2, elements #141 are electrically connected to element #111, paragraph [0080], rows 3-7); protrusion patterns extending upwardly on portions of the respective redistribution patterns (Fig.2, element #142); a second insulating layer provided on the first insulating layer to cover the redistribution wirings and expose upper surfaces of the protrusion patterns (Fig.2, element #132a, paragraph [0107], rows 1-2); and under bump metallurgy (UBM) pads extending on the upper surfaces of the protrusion patterns (Fig.2, elements #150, paragraph [0086], rows 1-2); and conductive bumps extending on the UBM pads of the redistribution wiring layer (Fig.2, elements #160).
Regarding claim 2, Kim_059 teaches the semiconductor package of claim 1 as set forth in the anticipation rejection. Kim_059 further teaches the semiconductor package of Claim 1, wherein each UBM pad extends on a first portion of the upper surface of a corresponding protrusion pattern (Fig.2, elements #150 extend on a portion of the upper surface of elements #142).
Regarding claim 4, Kim_059 teaches the semiconductor package of claims 1 and 2 as set forth in the anticipation rejection. Kim_059 further teaches the semiconductor package of the semiconductor package of Claim 2, wherein the first portion of the upper surface of the protrusion pattern is a central region on the upper surface of the protrusion pattern (Fig.2, element #150 extends in a central region of the upper surface of element #142).
Regarding claim 6, Kim_059 teaches the semiconductor package of claim 1 as set forth in the anticipation rejection. Kim_059 further teaches the semiconductor package of Claim 1 wherein an upper surface of the second insulating layer is coplanar with the upper surface of the protrusion patterns (Fig.8, upper surface of element #132a is coplanar with the upper surface of element #142).
Regarding claim 8, Kim_059 teaches the semiconductor package of claim 1 as set forth in the anticipation rejection. Kim_059 further teaches the semiconductor package of Claim 1, wherein the second insulating layer includes a thermosetting resin or a polyimide (insulator layer includes polyimide, paragraph [0070], rows 1-9) .
Regarding claim 9, Kim_059 teaches the semiconductor package of claim 1 as set forth in the anticipation rejection. Kim_059 further teaches the semiconductor package of Claim 1, wherein the UBM pad and the protrusion pattern include copper (paragraph [0081], rows 1-4, and paragraph [0086], rows 1-3) and the conductive bump includes solder (paragraph [0090], rows 1-2).
Regarding claim 10, Kim_059 teaches the semiconductor package of claim 1 as set forth in the anticipation rejection. Kim_059 further teaches the semiconductor package of Claim 1, further comprising: a molding member covering a side surface of the semiconductor chip (Fig.2, element #120, paragraph [0241], rows 1-3, covers a lateral side of the chip, element #110); and wherein the redistribution wiring layer extends on a lower surface of the molding member to thereby cover the first surface of the semiconductor chip (Fig.2, element #130 extends on the surface of element #120, right below and in contact with the bottom surface of element #110, and covers the top surface of element #110).
Regarding claim 11, Kim_059 teaches a semiconductor package, comprising: a semiconductor chip (Fig.2, element #110) having chip pads on a first surface thereof (Fig.2, pads, elements #111, are located on the top surface of element #110); a redistribution wiring layer that at least partially covers the first surface of the semiconductor chip (Fig.2, element #130), and has redistribution wirings that are electrically connected to the chip pads (Fig.2, elements #141 are electrically connected to elements #111, paragraph [0080], rows 3-7); and electrically conductive bumps that extend on an outer surface of the redistribution wiring layer, and are electrically connected to the redistribution wirings (Fig.2, element #160); wherein the redistribution wiring layer comprises: a protrusion pattern provided on at least one insulating layer (Fig.2, element #142 is provided on top of insulating layer, element #131a, paragraph [0107], rows 1-2); and extending upwardly on at least a portion of an uppermost redistribution wiring among the redistribution wirings (Fig.2, element #142 extends upwardly on a portion of the uppermost wiring, element #141); a protective layer covering the redistribution wirings on the at least one insulating layer and exposing an upper surface of the protrusion pattern (Fig.2, element #132a, paragraph [0107], rows 1-2); and a bonding pad extending on the upper surface of the protrusion pattern (Fig.2, elements #150, paragraph [0086], rows 1-2) and wherein an electrically conductive bump extends on the bonding pad (Fig.2, element #160 extends on element #150).
Regarding claim 12, Kim_059 teaches the semiconductor package of claim 11 as set forth in the anticipation rejection. Kim_059 further teaches the semiconductor package of Claim 11, wherein the bonding pad extends on a portion of the upper surface of the protrusion pattern (Fig.2, element #150 extends on a portion of the upper surface of element #142).
Regarding claim 16, Kim_059 teaches the semiconductor package of claim 11 as set forth in the anticipation rejection. Kim_059 further teaches the semiconductor package of claim 11, wherein an upper surface of the protective layer is coplanar with the upper surface of the protrusion pattern (Fig.2, upper surface of element #132a is coplanar with the upper surface of element #142).
Regarding claim 17, Kim_059 teaches the semiconductor package of claim 11 as set forth in the anticipation rejection. Kim_059 further teaches the semiconductor package of Claim 11, wherein the protective layer includes a thermosetting resin or a polyimide (element #132a includes polyimide, paragraph [0070], rows 1-9).
Regarding claim 18, Kim_059 teaches the semiconductor package of claim 11 as set forth in the anticipation rejection. Kim_059 further teaches the semiconductor package of Claim 11, wherein the bonding pad and the protrusion pattern includes copper (paragraph [0081], rows 1-4, and paragraph [0086], rows 1-3), and the conductive bump includes solder(paragraph [0090], rows 1-2).
Regarding claim 19, Kim_059 teaches the semiconductor package of claim 11 as set forth in the anticipation rejection. Kim_059 further teaches the semiconductor package of Claim 11, further comprising: a molding member covering a side surface of the semiconductor chip (Fig.2, element #120, paragraph [0241], rows 1-3, covers a lateral side of the chip, element #110); and wherein the redistribution wiring layer extends on a lower surface of the molding member, and covers the first surface of the semiconductor chip (Fig.2, element #130 extends on the surface of element #120 right below and in contact with bottom surface of element #110, and covers the top surface of element #110).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim_059, in view of Kim et al., (United States Patent Number, US 10,692,818 B2) hereinafter referenced as Kim_818.
Regarding claim 3, Kim_059 teaches the semiconductor package of claims 1 and 2 as set forth in the anticipation rejection. Kim_059 does not teach further the semiconductor package of Claim 2, wherein each conductive bump is in direct contact with a second portion of the upper surface of the corresponding protrusion that is exposed by the UBM pad. Kim_818 teaches, wherein each conductive bump (Fig.15, rotated vertically by 180 degrees, elements #170D, #170E and #170F) is in direct contact with a second portion of the upper surface of the corresponding protrusion that is exposed by the UBM pad (Fig.15, rotated vertically by 180 degrees, elements #170 are in direct contact with the portion of the upper surface of the protrusion, element #142, that is exposed by elements #160D, #160E and #160F). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kim_818 and disclose each conductive bump is in direct contact with a second portion of the upper surface of the corresponding protrusion that is exposed by the UBM pad. As disclosed by Kim_818, this structure allows one to control the height of the conductive bumps, and therefore control the warpage of the semiconductor package (column 16, rows 15-26).
Regarding claim 14, Kim_059 teaches the semiconductor package of claims 11 and 12 as set forth in the anticipation rejection. Kim_059 further teaches wherein the bonding pad covers a central region of the upper surface of the protrusion pattern (Fig.2, element #150 cover a central region). Kim_059 does not teach wherein the bonding pad exposes a ring-shaped surrounding region of the upper surface of the protrusion pattern. Kim_818 teaches wherein the bonding pad covers a central region of the upper surface of the protrusion pattern, but exposes a ring-shaped surrounding region of the upper surface of the protrusion pattern (Fig.15, element #160D, exposes a ring-shapes surrounding region of the protrusion pattern, element #142). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kim_818 and disclose the bonding pad exposes a ring-shaped surrounding region of the upper surface of the protrusion pattern. As disclosed by Kim_818, this geometry allows one to control the height of the conductive bumps, and therefore control the warpage of the semiconductor package (column 16, rows 15-26).
Claim 5, 7, 13, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim_059.
Regarding claim 5, Kim_059 teaches the semiconductor package of claim 1 as set forth in the anticipation rejection. In a different embodiment, Kim_059 teaches the semiconductor package of Claim 1, wherein an entire lower surface of each UBM pad is bonded to the upper surface of the corresponding protrusion pattern (Fig.8, the entire lowest surface of UBM, element #150b, is bonded to the upper surface of corresponding element #142). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Kim_059 and disclose an entire lower surface of each UBM pad is bonded to the upper surface of the corresponding protrusion pattern. This maximizes the contact area between the pad and the protrusion, making the electrical connection more reliable.
Regarding claim 7, Kim_059 teaches the semiconductor package of claim 1 as set forth in the anticipation rejection. Kim_059 further teaches the semiconductor the semiconductor package of Clam 1, wherein the UBM pad has a diameter of at least 5 pm (paragraph [0092], rows 20-24). The claimed range overlaps the value disclosed by Kim_059 and therefore a prima facie case of obviousness exists (MPEP 2144.05).
Regarding claim 13, Kim_059 teaches the semiconductor package of claims 11 and 12 as set forth in the anticipation rejection. In a different embodiment Kim_059 teaches a portion of the upper surface of the protrusion pattern exposed by the bonding pad (Fig.8, a portion of the upper surface of the protrusion pattern is exposed by the bonding pad, element #150b). Thus, both embodiments teach a structure of a terminal capable of transmitting signals to or from a semiconductor device. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the structure showed in Fig.2 could have been replaced with the structure showed in Fig.8, because both serve the same purpose of transmitting signals to or from a semiconductor device. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing a terminal capable of transmitting signals to or from a semiconductor device. The extra insulator layer of the terminal showed in Fig.8, can be optimized for the adhesion between the conductive bump and the insolation structure protecting the wiring.
Kim_059 further teaches the semiconductor package of Claim 12, wherein the electrically conductive bump completely covers a portion of the upper surface of the protrusion pattern exposed by the bonding pad (Fig.8, element #160 completely covers element #150, paragraph [0090], rows 1-8, and therefore completely covers the portion of the upper surface of element #142 exposed by element #150 as showed in Fig.8).
Regarding claim 15, Kim_059 teaches the semiconductor package of claim 11 as set forth in the anticipation rejection. In a different embodiment, Kim_059 teaches the semiconductor package of Claim 11, wherein an entire lower surface of the bonding pad is bonded to the upper surface of the protrusion pattern (Fig.8, the entire lowest surface of UBM, element #150b, is bonded to the upper surface of corresponding element #142). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Kim_059 and disclose an entire lower surface of each UBM pad is bonded to the upper surface of the corresponding protrusion pattern. This maximizes the contact area between the pad and the protrusion, making the electrical connection more reliable.
Regarding claim 20, Kim_059 teaches a semiconductor package, comprising: a redistribution wiring layer having a first surface and a second surface extending opposite to the first surface (Fig.2, element #130, first surface is the bottom surface and second surface is the top surface), the redistribution wiring layer including at least one insulating layer (Fig.2, element #131a, paragraph [0107], rows 1-2) and redistribution wirings provided in the at least one insulating layer (Fig.2, element #114); a semiconductor chip disposed on the first surface of the redistribution wiring layer (Fig.2, element #110 is disposed on the bottom surface of element #130), the semiconductor chip having chip pads that are electrically connected to the redistribution wirings (Fig.2, elements #111 are electrically connected to elements #114, paragraph [0080], rows 3-7); and outer connection members disposed on the second surface of the redistribution wiring layer the outer connection members electrically connected to the redistribution wirings (Fig.2, element #160); wherein an uppermost redistribution wiring among the redistribution wirings includes a redistribution pattern extending on the at least one insulating layer (Fig.2, element #114, extends in layers #131a) and a protrusion pattern extending upwardly on a portion of the redistribution pattern (Fig.2, element #142); wherein the redistribution wiring layer further comprises: a protective layer provided on the at least one insulating layer and covering the uppermost redistribution wirings and exposing an upper surface of the protrusion pattern (Fig.2, element #132a, paragraph [0107], rows 1-2); and a bonding pad disposed on the upper surface of the protrusion pattern (Fig.2, element #150); and wherein the outer connection member extends on the bonding pad (Fig.2, element #160 extends on element #150).
In a different embodiment, Kim_059 teaches a portion of the upper surface of the protrusion pattern exposed by the bonding pad (Fig.8, a portion of the upper surface of the protrusion pattern is exposed by the bonding pad, element #150b). Thus, both embodiments teach a structure of a terminal capable of transmitting signals to or from a semiconductor device. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the structure showed in Fig.2 could have been replaced with the structure showed in Fig.8, because both serve the same purpose of transmitting signals to or from a semiconductor device. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing a terminal capable of transmitting signals to or from a semiconductor device. The extra insulator layer of the terminal showed in Fig.8, can be optimized for the adhesion between the conductive bump and the insolation structure protecting the wiring.
Kim_059 further teaches, wherein the electrically conductive bump completely covers a portion of the upper surface of the protrusion pattern exposed by the bonding pad (Fig.8, element #160 completely covers element #150, paragraph [0090], rows 1-8, and therefore completely covers the portion of the upper surface of element #142 exposed by element #150 as shown in Fig.8).
Conclusion
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899