DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 04/24/2026 has been entered. Claims 1, 4-11, 14-17 19, 20 and newly added claim 21, remain pending in the application. Claims 2, 3, 12, 13 and 18 have been cancelled. Applicant’s amendment has overcome the 112(b) rejection previously set forth in the Non-Final Office Action mailed on 02/04/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 5, 8, 9, 11, 14, 15, 17, 20 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seo et al., (United States Patent Number, US 9,831,202 B2), hereinafter referenced as Seo.
Regarding claim 1, Seo teaches a semiconductor package, comprising: a semiconductor chip (Fig.6, element #110 has chips, column 5, rows 47-50) having chip pads extending adjacent a first surface thereof (Fig.6, element #122A, adjacent to top surface of element #110); a redistribution wiring layer covering at least a portion of the first surface of the semiconductor chip, said redistribution wiring layer including: redistribution wirings with redistribution patterns provided on a first insulating layer and electrically connected to the chip pads (Fig.6, element #192 is electrically connected to pad #122A and provided of insulating layer #124A); protrusion patterns extending upwardly on portions of the respective redistribution patterns (Fig.6, formed by elements #130, #152 and #154); a second insulating layer provided on the first insulating layer to cover the redistribution wirings and expose upper surfaces of the protrusion patterns (Fig.6, element #194); and under bump metallurgy (UBM) pads extending on the upper surfaces of the protrusion patterns (Fig.6, element #156); and conductive bumps extending on the UBM pads of the redistribution wiring layer (Fig.6, element #160), wherein each UBM pad extends on a first portion of the upper surface of a corresponding protrusion pattern (Fig.6, each element #156 extends on a portion of the upper surface of element #154 located below element #156), and wherein each conductive bump is in direct contact with a second portion of the upper surface of the corresponding protrusion pattern that is exposed by the UBM pad (Fig.6, element #160 is in contact with exposed upper surface of element #154).
Regarding claim 4, Seo teaches the semiconductor package of claim 1 as set forth in the anticipation rejection. Seo further teaches the semiconductor package of Claim 1, wherein the first portion of the upper surface of the protrusion pattern is a central region on the upper surface of the protrusion pattern (Fig.6, the portion covered by element #156 is a central portion).
Regarding claim 5, Seo teaches the semiconductor package of claim 1 as set forth in the anticipation rejection. Seo further teaches the semiconductor package of Claim 1, wherein the UBM pad is planar and an entire lower surface of each UBM pad is bonded to the upper surface of the corresponding protrusion pattern (Fig.6, element #156 is planar and entire lower surface is bonded to the upper surface of element #154).
Regarding claim 8, Seo teaches the semiconductor package of claim 1 as set forth in the anticipation rejection. Seo further teaches the semiconductor package of Claim 1, wherein the second insulating layer includes a thermosetting resin or a polyimide (column 13, row 55).
Regarding claim 9, Seo teaches the semiconductor package of claim 1 as set forth in the anticipation rejection. Seo further teaches the semiconductor package of Claim 1, wherein the UBM pad (column 6, rows 46-47), and the protrusion pattern include copper (column 6, rows 3-4 and 41-42), and the conductive bump includes solder (column 5, row 26-27).
Regarding claim 11, Seo teaches a semiconductor package, comprising: a semiconductor chip (Fig.6, element #110 has chips, column 5, rows 47-50) having chip pads on a first surface thereof (Fig.6, element #122A on top surface of element #110); a redistribution wiring layer that at least partially covers the first surface of the semiconductor chip, and has redistribution wirings that are electrically connected to the chip pads (Fig.6, element #192 is electrically connected to pads #122A and partially covers the upper surface of element #110); and electrically conductive bumps that extend on an outer surface of the redistribution wiring layer and are electrically connected to the redistribution wirings (Fig.6, element #160 is electrically connected to element #192 through elements #130, #152, #154 and #156); wherein the redistribution wiring layer comprises: a protrusion pattern provided on at least one insulating layer and extending upwardly on at least a portion of an uppermost redistribution wiring among the redistribution wirings (Fig.6, protrusion formed by elements #130, #152, #154, provide on layer element #124A); a protective layer covering the redistribution wirings on the at least one insulating layer and exposing an upper surface of the protrusion pattern (Fig.6, element #194); and a bonding pad extending on the upper surface of the protrusion pattern (Fig.6, element #156); and wherein an electrically conductive bump extends on the bonding pad (Fig.6, element #160 extends on element #156), wherein each UBM pad extends on a first portion of the upper surface of a corresponding protrusion pattern (Fig.6, portion of the upper surface of element #154 located below element #156), and wherein each conductive bump is in direct contact with a second portion of the upper surface of the corresponding protrusion pattern that is exposed by the UBM pad (Fig.6, element #160 is in contact with exposed upper surface of element #154).
Regarding claim 14, Seo teaches the semiconductor package of claim 11 as set forth in the anticipation rejection. Seo further teaches the semiconductor package of Claim 11 wherein the bonding pad covers a central region of the upper surface of the protrusion pattern, butthe portion covered by element #156 is a central portion and column 21, rows 48-54,and 59-64).
Regarding claim 15, Seo teaches the semiconductor package of claim 11 as set forth in the anticipation rejection. Seo further teaches the semiconductor package of Claim 11, wherein an entire lower surface of the bonding pad is bonded to the upper surface of the protrusion pattern (Fig.6, an entire lower surface of element #156 is bonded to the upper surface of element #154).
Regarding claim 17, Seo teaches the semiconductor package of claim 11 as set forth in the anticipation rejection. Seo further teaches the semiconductor package of Claim 11, wherein the protective layer includes a thermosetting resin or a polyimide (column 13, row 55).
Regarding claim 20, Seo teaches a semiconductor package, comprising: a redistribution wiring layer having a first surface and a second surface extending opposite to the first surface (Fig.6, element #192, has a top and a bottom surface), the redistribution wiring layer including at least one insulating layer and redistribution wirings provided in the at least one insulating layer (Fog.6, element #124A); a semiconductor chip disposed on the first surface of the redistribution wiring layer (Fig.6, element #110, column 5, rows 47-50 is disposed on the bottom surface of element #192), the semiconductor chip having chip pads that are electrically connected to the redistribution wirings (Fig.6, element #122A); and outer connection members disposed on the second surface of the redistribution wiring layer, the outer connection members electrically connected to the redistribution wirings (Fig.6, element #160); wherein an uppermost redistribution wiring among the redistribution wirings includes a redistribution pattern extending on the at least one insulating layer and a protrusion pattern extending upwardly on a portion of the redistribution pattern (Fig.6, part of element #192 extends on insulating layer #124A and protrusion formed by element #130, #152 and #154); wherein the redistribution wiring layer further comprises: a protective layer provided on the at least one insulating layer and covering the uppermost redistribution wirings and exposing an upper surface of the protrusion pattern (Fig.6, element #194); and a bonding pad disposed on the upper surface of the protrusion pattern (Fig.6, element #156); and wherein the outer connection member extends on the bonding pad and completely covers a portion of the protrusion pattern exposed by the bonding pad (Fig.6, element #160 extends on element #156 and completely covers the portion of element #154 exposed by element #156), wherein the bonding pad extends on a first portion of the upper surface of the protrusion pattern (Fig.6, portion of the upper surface of element #154 located below element #156), and wherein the outer connection member is in direct contact with a second portion of the upper surface of the protrusion pattern that is exposed by the bonding pad (Fig.6, element #160 is in contact with exposed upper surface of element #154).
Regarding claim 21, Seo teaches the semiconductor package of claim 1 as set forth in the anticipation rejection. Seo further teaches the semiconductor package of Claim 1, wherein the under bump metallurgy (UBM) pads are isolated from the first and second insulating layers (Fig.6, element #156 is isolated from layer #194 and #124A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7, 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Seo in view of Kim et al., (United States Patent Application Publication Number, US 2022/0352059 A1), hereinafter referenced as Kim_059.
Regarding claim 7, Seo teaches the semiconductor package of claim 1 as set forth in the anticipation rejection. Seo not teach the semiconductor package of Clam 1, wherein the UBM pad has a diameter of at least 5 um. Kim_059 teaches, wherein the UBM pad has a diameter of at least 5 um (paragraph [0092], rows 20-24). The claimed range overlaps the value disclosed by Kim_059 and therefore a prima facie case of obviousness exists (MPEP 2144.05). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kim_059 and disclose wherein the UBM pad has a diameter of at least 5 um. This provides a large enough contact area between the pad and the conductive bump UBM to achieve reliable electrical contacts.
Regarding claim 10, Seo teaches the semiconductor package of claim 1 as set forth in the anticipation rejection. Seo not teach the semiconductor package of Clam 1 further comprising: a molding member covering a side surface of the semiconductor chip; and wherein the redistribution wiring layer extends on a lower surface of the molding member to thereby cover the first surface of the semiconductor chip. Kim_059 teaches the semiconductor package of Claim 1, further comprising: a molding member covering a side surface of the semiconductor chip (Fig.2, element #120, paragraph [0241], rows 1-3, covers a lateral side of the chip, element #110); and wherein the redistribution wiring layer extends on a lower surface of the molding member to thereby cover the first surface of the semiconductor chip (Fig.2, element #130 extends on the surface of element #120, right below and in contact with the bottom surface of element #110, and covers the top surface of element #110). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kim_059 and disclose a molding member covering a side surface of the semiconductor chip; and wherein the redistribution wiring layer extends on a lower surface of the molding member to thereby cover the first surface of the semiconductor chip. Encapsulating chips using molding materials is well known in the art, and as disclosed by Kim_059, the molding materials is used to protect the chip from harmful environments (paragraph [0059], rows 9-11). As showed by Kim_059 in Fig.2, having the wiring layer extend over a surface of the molding member to thereby cover the first surface of the semiconductor chip allows one to redistribute the contacts on the surface of the package in order to provide adequate spacing between the contacts.
Regarding claim 19, Seo teaches the semiconductor package of claim 11 as set forth in the anticipation rejection. Seo not teach the semiconductor package the semiconductor package of Claim 11, further comprising: a molding member covering a side surface of the semiconductor chip; and wherein the redistribution wiring layer extends on a lower surface of the molding member, and covers the first surface of the semiconductor chip. Kim_059 teaches the semiconductor package of Claim 11, further comprising: a molding member covering a side surface of the semiconductor chip (Fig.2, element #120, paragraph [0241], rows 1-3, covers a lateral side of the chip, element #110); and wherein the redistribution wiring layer extends on a lower surface of the molding member to thereby cover the first surface of the semiconductor chip (Fig.2, element #130 extends on the surface of element #120, right below and in contact with the bottom surface of element #110, and covers the top surface of element #110). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kim_059 and disclose a molding member covering a side surface of the semiconductor chip; and wherein the redistribution wiring layer extends on a lower surface of the molding member to thereby cover the first surface of the semiconductor chip. Encapsulating chips using molding materials is well known in the art, and as disclosed by Kim_059, the molding materials is used to protect the chip from harmful environments (paragraph [0059], rows 9-11). As showed by Kim_059 in Fig.2, having the wiring layer extend over a surface of the molding member to thereby cover the first surface of the semiconductor chip allows one to redistribute the contacts on the surface of the package in order to provide adequate spacing between the contacts.
Claims 1, 6, 11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim_059 in view of Wook, (Korean Patent Application Publication Number, KR 20090089578 A), hereinafter referenced as Wook.
Regarding claim 1, Kim_059 teaches a semiconductor package, comprising: a semiconductor chip (Fig.2, element #110) having chip pads extending adjacent a first surface thereof (Fig.2, elements #111, adjacent to the top surface of element #110); a redistribution wiring layer covering at least a portion of the first surface of the semiconductor chip (Fig.2, element #130), said redistribution wiring layer including: redistribution wirings with redistribution patterns provided on a first insulating layer (Fig.2, parts of element #141 are provided on top of element #131a, paragraph [0107], rows 1-2) and electrically connected to the chip pads (Fig.2, elements #141 are electrically connected to element #111, paragraph [0080], rows 3-7); protrusion patterns extending upwardly on portions of the respective redistribution patterns (Fig.2, element #142); a second insulating layer provided on the first insulating layer to cover the redistribution wirings and expose upper surfaces of the protrusion patterns (Fig.2, element #132a, paragraph [0107], rows 1-2); and under bump metallurgy (UBM) pads extending on the upper surfaces of the protrusion patterns (Fig.2, elements #150, paragraph [0086], rows 1-2); and conductive bumps extending on the UBM pads of the redistribution wiring layer (Fig.2, elements #160).
Kim_059 does not teach wherein each UBM pad extends on a first portion of the upper surface of a corresponding protrusion pattern, and wherein each conductive bump is in direct contact with a second portion of the upper surface of the corresponding protrusion pattern that is exposed by the UBM pad. Wook teaches wherein each UBM pad (Fig.1, element #170) extends on a first portion of the upper surface of a corresponding protrusion pattern (Fig.1, element #170 extends on the upper surface of the protrusion, element #160) and wherein each conductive bump is in direct contact with a second portion of the upper surface of the corresponding protrusion pattern that is exposed by the UBM pad (Fig.2, element #180 is in direct contact with exposed upper surface of element #160). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Wook and disclose wherein each UBM pad extends on a first portion of the upper surface of a corresponding protrusion pattern, and wherein each conductive bump is in direct contact with a second portion of the upper surface of the corresponding protrusion pattern that is exposed by the UBM pad. As disclosed by Wook, this helps prevent the conductive bump from being separated from the rest of the package (page 5, last two rows).
Regarding claim 6, the combination of Kim_059 and Wook teaches the semiconductor package of claim 1, as set forth in the obviousness rejection. Kim_059 further teaches the semiconductor package of Claim 1 wherein an upper surface of the second insulating layer is coplanar with the upper surface of the protrusion patterns (Fig.6, upper surface of element #132a is coplanar with the upper surface of element #142).
Regarding claim 11, Kim_059 teaches a semiconductor package, comprising: a semiconductor chip (Fig.2, element #110) having chip pads on a first surface thereof (Fig.2, pads, elements #111, are located on the top surface of element #110); a redistribution wiring layer that at least partially covers the first surface of the semiconductor chip (Fig.2, element #130), and has redistribution wirings that are electrically connected to the chip pads (Fig.2, elements #141 are electrically connected to elements #111, paragraph [0080], rows 3-7); and electrically conductive bumps that extend on an outer surface of the redistribution wiring layer, and are electrically connected to the redistribution wirings (Fig.2, element #160); wherein the redistribution wiring layer comprises: a protrusion pattern provided on at least one insulating layer (Fig.2, element #142 is provided on top of insulating layer, element #131a, paragraph [0107], rows 1-2); and extending upwardly on at least a portion of an uppermost redistribution wiring among the redistribution wirings (Fig.2, element #142 extends upwardly on a portion of the uppermost wiring, element #141); a protective layer covering the redistribution wirings on the at least one insulating layer and exposing an upper surface of the protrusion pattern (Fig.2, element #132a, paragraph [0107], rows 1-2); and a bonding pad extending on the upper surface of the protrusion pattern (Fig.2, elements #150, paragraph [0086], rows 1-2) and wherein an electrically conductive bump extends on the bonding pad (Fig.2, element #160 extends on element #150),
Kim_059 does not teach wherein each UBM pad extends on a first portion of the upper surface of a corresponding protrusion pattern, and wherein each conductive bump is in direct contact with a second portion of the upper surface of the corresponding protrusion pattern that is exposed by the UBM pad. Wook teaches wherein each UBM pad (Fig.1, element #170) extends on a first portion of the upper surface of a corresponding protrusion pattern (Fig.1, element #170 extends on the upper surface of the protrusion, element #160) and wherein each conductive bump is in direct contact with a second portion of the upper surface of the corresponding protrusion pattern that is exposed by the UBM pad (Fig.2, element #180 is in direct contact with exposed upper surface of element #160). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Wook and disclose wherein each UBM pad extends on a first portion of the upper surface of a corresponding protrusion pattern, and wherein each conductive bump is in direct contact with a second portion of the upper surface of the corresponding protrusion pattern that is exposed by the UBM pad. As disclosed by Wook, this helps prevent the conductive bump from being separated from the rest of the package (page 5, last two rows).
Regarding claim 16, the combination of Kim_059 and Wook teaches the semiconductor package of claim 11, as set forth in the obviousness rejection. Kim_059 further teaches the semiconductor package of Claim 11 wherein an upper surface of the protective layer is coplanar with the upper surface of the protrusion pattern (Fig.6, upper surface of element #132a is coplanar with the upper surface of element #142).
Response to Arguments
Applicant’s arguments filed on 04/24/2026 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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