Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21-27, 29-37, and 39 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JEUNG B. S. et al, US 20030116861 A1.
Jeung teaches:
A semiconductor package comprising:
a signal distribution structure (SDS) comprising a dielectric layer (524a) and a conductive layer (541b), the signal distribution structure comprising a top SDS side and a bottom SDS side; Figure 5
a first semiconductor die (120) comprising a first top die side and a first bottom die side (figure 5), wherein:
the first bottom die side is coupled to the top SDS side (figure 5); and
the first bottom die side comprises a die bond pad (123) coupled to the conductive layer (541b); (figure 5)
a package attachment structure (116) coupled to the bottom SDS side and electrically coupled to the die bond pad (123) through the conductive layer (541b);
a first encapsulating material (512) comprising a first top encapsulant side and a first bottom encapsulant side, wherein the first encapsulating material (512) laterally surrounds the first semiconductor die (120) and covers a portion of the top SDS side; (figure 5) and
a second encapsulating material (524b) comprising a second top encapsulant side and a second bottom encapsulant side (figure 5b), wherein the second encapsulating material (524b) laterally surrounds the package attachment structure (116) and covers a portion of the bottom SDS side. See figure 5 and para [0030-0032]
22. (Previously Presented) The semiconductor package of claim 21, further comprising a vertical interconnect (540) having a top side and a bottom side, (figure 5) wherein:
the vertical interconnect (540) runs vertically entirely through the first encapsulating material (512) between the first top encapsulant side and the first bottom encapsulant side; (figure 5) and
the vertical interconnect (540) is electrically connected to the die bond pad (123) through the conductive layer (541b). Figure 5
23. (Previously Presented) The semiconductor package of claim 22, further comprising a second semiconductor die (130) over the first top die side (figure 5) and electrically coupled to the vertical interconnect (540). Figure 5
24. (Previously Presented) The semiconductor package of claim 22, wherein the top side of the vertical interconnect (540) is coplanar with the first top encapsulant side. (Figure 5)
25. (Previously Presented) The semiconductor package of claim 21, wherein the package attachment structure (161) comprises a conductive bump. (para 23 and 31)
27. (Previously Presented) The semiconductor package of claim 21, wherein the second encapsulating material (524b) contacts the package attachment structure (161). Figure 5
28. (Previously Presented) The semiconductor package of claim 21, wherein the first encapsulating material (524a) extends between the first bottom die side and the top SDS side. Figure 5
29. (Previously Presented) The semiconductor package of claim 21, further comprising under bump metal between the conductive layer and the package attachment structure. (para 23)
31. (Previously Presented) A method of making a semiconductor package, the method comprising:
providing a signal distribution structure (SDS) comprising a dielectric layer (524a) and a conductive layer (541b), the signal distribution structure comprising a top SDS side and a bottom SDS side; (figure 5)
providing a first semiconductor die (120) comprising a first top die side and a first bottom die side, (figure 5) wherein:
the first bottom die side is coupled to the top SDS side; (figure 5)
and the first bottom die side comprises a die bond pad (123) coupled to the conductive layer (541b); (figure 5)
providing a package attachment structure (161) coupled to the bottom SDS side and electrically coupled to the die bond pad (123) through the conductive layer (541b); (figure 5)
providing a first encapsulating material (512) comprising a first top encapsulant side and a first bottom encapsulant side, (figure 5) wherein the first encapsulating material laterally surrounds the first semiconductor die (120) and covers a portion of the top SDS side; (figure 5) and
providing a second encapsulating material (524b) comprising a second top encapsulant side and a second bottom encapsulant side, (figure 5) wherein the second encapsulating material (524b) laterally surrounds the package attachment structure (161) and covers a portion of the bottom SDS side. Figure 5 (para 0030-0032)
32. (Previously Presented) The method of claim 31, further comprising providing a vertical interconnect (540) having a top side and a bottom side, wherein:
the vertical interconnect (540) runs vertically entirely through the first encapsulating material (512) between the first top encapsulant side and the first bottom encapsulant side; (figure 5) and
the vertical interconnect (540) is electrically connected to the die bond pad (123) through the conductive layer (541b). Figure 5
33. (Previously Presented) The method of claim 32, wherein the top side of the vertical interconnect is coplanar with the first top encapsulant side. Figure 5
34. (Previously Presented) The method of claim 31, wherein the package attachment structure (161) comprises a conductive bump and/or a conductive pillar. (para 23)
35. (Previously Presented) The method of claim 31, wherein the second encapsulating material (524b) contacts the package attachment structure (161). Figure 5
36. (Previously Presented) The method of claim 31, wherein the first encapsulating material (524a) extends between the first bottom die side and the top SDS side. Figure 5
37. (Previously Presented) The method of claim 31, further comprising providing under bump metal between the conductive layer (541b) and the package attachment structure (161). Para 23
39. (Currently Amended) A semiconductor package comprising:
a signal distribution structure (SDS) comprising a dielectric layer (524a) and a conductive layer (541b), the signal distribution structure comprising a top SDS side and a bottom SDS side; (Figure 5)
a semiconductor die (120) comprising a top die side and a bottom die side, wherein: (Figure 5)
the bottom die side is coupled to the top SDS side; (figure 5) and
the bottom die side comprises a die bond pad (123) coupled to the conductive layer (541b); (figure 5)
a package attachment structure (161) coupled to the bottom SDS side and electrically coupled to the die bond pad (123) through the conductive layer (541b); Figure 5
a first encapsulating material (512) comprising a first top encapsulant side and a first bottom encapsulant side, (figure 5) wherein the first encapsulating material laterally surrounds the semiconductor die (120) and covers a portion of the top SDS side; (figure 5)
a second encapsulating material (524b) comprising a second top encapsulant side and a second bottom encapsulant side, (figure 5) wherein the second encapsulating material (524b) laterally surrounds the package attachment structure (161) and covers a portion of the bottom SDS side; (figure 5) and
a vertical interconnect (540) comprising a top side and a bottom side, (figure 5) wherein the vertical interconnect extends through the first encapsulating material (512) and is electrically connected to the conductive layer (541b). Figure 5 (para 0030-0032)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 26 , 38 and 40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeung et al.
Jueng fails to teach:
wherein:
the package attachment structure comprises a conductive bump and/or a conductive pillar, and
over half of a height of the package attachment structure is encapsulated by the second encapsulating material.
Jeung teaches:
a flowable conductive material 116, such as solder, can be disposed on the assembly connection sites 114 to form solder balls or other terminal structures. In one aspect of this embodiment, the connection sites can have a wetting layer formed from materials such as gold or a nickel-gold alloy to readily receive the flowable conductive material 116. (para 0023)
Jeung is silent to the height of the (second) encapsulant.
In regards to the height of the encapsulant, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize this through routine experimentation and would not lend itself to patentability in the instant application, without displaying unexpected results. (in Re Aller)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Pu et al, US 7,208,825 and Kulichi et al US 8,710,639 in combination with Camacho et al, US 2009/0140441 teach the claimed invention.
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/ Primary Examiner, Art Unit 2893
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