DETAILED ACTION
Claim Objections
1. The numbering of claims 27 – 33, pages 6, 7 of claim set are not in accordance with 37 CFR 1.126 which requires the original numbering of the claims to be preserved throughout the prosecution.
The numbered orders of claims 27 – 33, pages 6, 7 are objected as being a substantial duplicate of number orders of claims 27 – 29, pages 5, 6.
The numbered claims 27 – 33, pages 6, 7 of claim set been renumbered 30 - 36, respectively.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 4, 14, 29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Curatola et al. (2019/0280093).
With regard to claim 1, Curatola et al. disclose a semiconductor device (for example, figure 1) comprising:
a substrate (116) of a first semiconductor material (for example, paragraph [0023]);
a conductive barrier structure (a conductive barrier layer 104 functioning as a conductive barrier structure) on the substrate (116);
a channel layer (106) of a second semiconductor material on the conductive barrier structure (104);
a barrier layer (108) on the channel layer (106), in which the channel layer (106) is between the barrier layer (108) and the conductive barrier structure (104); and a
gate (126) over the barrier layer (108) opposing the channel layer (106);
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With regard to claim 2, Curatola et al. disclose the channel layer (106) is inherently configured to conduct a charge of a first polarity; and the conductive barrier structure (104) is inherently configured to conduct a charge of a second polarity opposite from the first polarity (for example, paragraph [0059] discloses GaN may be combined with AlGaN or InGaN to form an electron gas inversion region as the channel. The semiconductor device 100 may have AlInN/AlN/GaN barrier/spacer/channel layer structures. In general, the normally-off compound semiconductor transistor can be realized using any suitable III-nitride technology such as GaN that permits the formation of opposite polarity inversion regions due to piezoelectric effects).
With regard to claim 3, Curatola et al. disclose the conductive barrier structure (104) includes an Aluminum Gallium Nitride (AlGaN) layer (for example, paragraphs [0024], [0059]).
With regard to claim 4, Curatola et al. disclose the first semiconductor material includes silicon, and the second semiconductor material includes Gallium Nitride (for example, see paragraph [0023]).
With regard to claim 14, Curatola et al. disclose a gate structure (126) comprising a first gate (referred to as “126A” by examiner’s annotation shown in fig. 1 below; wherein the gate portion 126A functioning a first gate) and a second gate (referred to as “126B” by examiner’s annotation shown in fig. 1 below; wherein the gate portion 126B functioning a second gate) over the barrier layer (108) opposing the channel layer (106); and a first electrical contact (referred to as “132A” by examiner’s annotation shown in fig. 1 below; wherein the first electrical contact 132A is a portion of the electrical contact 132) on a surface of the barrier layer (108) and a second electrical contact (118) on the surface of the barrier layer (108), the first gate (126A) is on a region in the channel layer (106).
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With regard to claim 29, Curatola et al. disclose a semiconductor device (for example, figure 1) comprising:
a substrate (116) of a first semiconductor material (for example, paragraph [0023]);
a conductive barrier structure (a conductive barrier layer 104 functioning as a conductive barrier structure) on the substrate (116);
a channel layer (106) of a second semiconductor material on the conductive barrier structure (104);
a barrier layer (108) on the channel layer (106), in which the channel layer (106) is between the barrier layer (108) and the conductive barrier structure (104); and a
gate (126) over the barrier layer (108) opposing the channel layer (106);
a gate structure (126) comprising a first gate (referred to as “126A” by examiner’s annotation shown in fig. 1 below; wherein the gate portion 126A functioning a first gate) and a second gate (referred to as “126B” by examiner’s annotation shown in fig. 1 below; wherein the gate portion 126B functioning a second gate) over the barrier layer (108) opposing the channel layer (106); and a first electrical contact (referred to as “132A” by examiner’s annotation shown in fig. 1 below; wherein the first electrical contact 132A is a portion of the electrical contact 132) and a second electrical contact (118) on a surface of the barrier layer (108), in which the first gate (126A) and the second gate (126B) are between the first electrical contact (132A) and the second electrical contact (118).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 - 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Curatola et al. (20190280093) in view of Kushida et al. (10680091).
With regard to claim 6, Curatola et al. do not clearly disclose the conductive barrier structure includes a quantum well configured to confine a first charge having an opposite polarity from a second charge that the channel layer is configured to conduct.
However, Kushida et al. discloses the conductive barrier structure (21, 22) includes a quantum well (22) configured to confine a first charge having an opposite polarity (p-type) from a second charge (i-type) that the channel layer (24) is configured to conduct. (for example, see fig. 7).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Curatola et al.’s device to have the conductive barrier structure includes a quantum well configured to confine a first charge having an opposite polarity from a second charge that the channel layer is configured to conduct as taught by Kushida et al. in order to enhance the strength of electric field between the drain portion and the source portion for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claims 7 - 9, Curatola et al. do not clearly disclose an electrical contact that penetrates through the barrier layer; wherein: the electrical contact is a first electrical contact; the semiconductor device further comprises a second electrical contact; the gate and the second electrical contact are on a region in the channel layer; and the first electrical contact is outside the region wherein: the electrical contact is a first electrical contact; the semiconductor device further comprises a second electrical contact and a third electrical contact on two sides of the gate; and the first electrical contact is electrically coupled to the gate.
However, Kushida et al. discloses an electrical contact (102) that penetrates through the barrier layer (21); wherein: the electrical contact (102) is a first electrical contact; the semiconductor device further comprises a second electrical contact (104); the gate (103) and the second electrical contact (104) are on a region in the channel layer (24); and the first electrical contact (102) is outside the region; or wherein: the electrical contact (102) is a first electrical contact; the semiconductor device further comprises second and third electrical contacts (104) on two sides of the gate (103); and the first electrical contact (102) is electrically coupled (couple via channel layer 24) to the gate (103).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Curatola et al.’s device to have an electrical contact that penetrates through the barrier layer; wherein: the electrical contact is a first electrical contact; the semiconductor device further comprises a second electrical contact; the gate and the second electrical contact are on a region in the channel layer; and the first electrical contact is outside the region wherein: the electrical contact is a first electrical contact; the semiconductor device further comprises a second electrical contact and a third electrical contact on two sides of the gate; and the first electrical contact is electrically coupled to the gate as taught by Kushida et al. in order to enhance the electrical connection efficiency between the drain portion and the source portion, as is known to one of ordinary skill in the art.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 33 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 4, 6 – 10, 12 – 14, 17 – 32 of copending Application No. 18/326,698 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim 1 of current Application is corresponding to claim 1 of Application No. 18/326,698 which filed on 11/24/25.
Claim 2 of current Application is corresponding to claim 2 of Application No. 18/326,698 which filed on 11/24/25.
Claim 3 of current Application is corresponding to claim 3 of Application No. 18/326,698 which filed on 11/24/25.
Claim 4 of current Application is corresponding to claim 4 of Application No. 18/326,698 which filed on 11/24/25.
Claim 5 of current Application is corresponding to claims 1, 17, 21 of Application No. 18/326,698 which filed on 11/24/25.
Claim 6 of current Application is corresponding to claim 6 of Application No. 18/326,698 which filed on 11/24/25.
Claim 7 of current Application is corresponding to claim 7 of Application No. 18/326,698 which filed on 11/24/25.
Claim 8 of current Application is corresponding to claim 8 of Application No. 18/326,698 which filed on 11/24/25.
Claim 9 of current Application is corresponding to claim 9 of Application No. 18/326,698 which filed on 11/24/25.
Claim 10 of current Application is corresponding to claim 10 of Application No. 18/326,698 which filed on 11/24/25 wherein a trench functioning as an isolation structure.
Claim 11 of current Application is corresponding to claim 10 of Application No. 18/326,698 which filed on 11/24/25 wherein a trench functioning as an isolation structure.
Claims 12, 13 of current Application is corresponding to claim 11 of Application No. 18/326,698 which filed on 11/24/25. It is inherently that a power or voltage signal functions as bias wherein the bias circuit includes at least one of: a resistive divider, or a minimum voltage selector for connecting the first and second contacts and substrate in order to perform the semiconductor device.
Claim 14 of current Application is corresponding to claim 12 of Application No. 18/326,698 which filed on 11/24/25 wherein a trench functioning as an isolation structure.
Claim 15 of current Application is corresponding to claim 13 of Application No. 18/326,698 which filed on 11/24/25 wherein a trench functioning as an isolation structure.
Claim 16 of current Application is corresponding to claim 14 of Application No. 18/326,698 which filed on 11/24/25 wherein a trench functioning as an isolation structure.
Claim 17 of current Application is corresponding to claim 17 of Application No. 18/326,698 which filed on 11/24/25 wherein a trench functioning as an isolation structure.
Claim 18 of current Application is corresponding to claim 18 of Application No. 18/326,698 which filed on 11/24/25.
Claim 19 of current Application is corresponding to claim 19 of Application No. 18/326,698 which filed on 11/24/25.
Claim 20 of current Application is corresponding to claim 20 of Application No. 18/326,698 which filed on 11/24/25.
Claim 21 of current Application is corresponding to claim 21 of Application No. 18/326,698 which filed on 11/24/25.
Claim 22 of current Application is corresponding to claim 22 of Application No. 18/326,698 which filed on 11/24/25. It is inherently that a semiconductor layer including injection layer in order to secure the electron mobility efficiency.
Claim 23 of current Application is corresponding to claim 23 of Application No. 18/326,698 which filed on 11/24/25.
Claim 24 of current Application is corresponding to claim 24 of Application No. 18/326,698 which filed on 11/24/25.
Claim 25 of current Application is corresponding to claim 25 of Application No. 18/326,698 which filed on 11/24/25.
Claim 26 of current Application is corresponding to claim 17 of Application No. 18/326,698 which filed on 11/24/25.
Claim 29 of current Application is corresponding to claim 26 of Application No. 18/326,698 which filed on 11/24/25.
Claim 27 (a second claim 27), page 5 in claim set of current Application is corresponding to claim 27 of Application No. 18/326,698 which filed on 11/24/25.
Claim 28 (a second claim 28), page 6 in claim set of current Application is corresponding to claim 28 of Application No. 18/326,698 which filed on 11/24/25.
Claim 29 (a second claim 29), page 6 in claim set of current Application is corresponding to claim 29 of Application No. 18/326,698 which filed on 11/24/25.
Claim 30, pages 6, 7 in claim set of current Application is corresponding to claim 30 of Application No. 18/326,698 which filed on 11/24/25.
Claim 31, page 7 in claim set of current Application is corresponding to claim 31 of Application No. 18/326,698 which filed on 11/24/25.
Claim 32, page 7 in claim set of current Application is corresponding to claim 30 of Application No. 18/326,698 which filed on 11/24/25.
Claim 33, page 7 in claim set of current Application is corresponding to claim 32 of Application No. 18/326,698 which filed on 11/24/25.
Allowable Subject Matter
7. Claims 17 – 28 in pages 4 - 6, claims 27 – 33, pages 6, 7 of claim set (Notably, allowable claims 27 - 33 assumed to be claim 30 - 36 based on a renumber of the objection) are allowable if a terminal disclaimer filing to overcome, because none of these references disclose or can be combined to yield the claimed invention such as an isolation structure between a respective first portion of the barrier layer, the channel layer, and the conductive barrier structure and a respective second portion of the barrier layer, the channel layer, and the conductive barrier structure; a first gate over the first portion of the barrier layer opposing the channel layer; a first electrical contact on a surface of the first portion of the barrier layer opposing the channel layer; a second gate over the second portion of the barrier layer opposing the channel layer; and a second electrical contact on a surface of the second portion of the barrier layer opposing the channel layer, in which the second electrical contact is electrically coupled to the first electrical contact as recited in claim 17.
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812