DETAILED ACTION
Claim Rejections - 35 USC § 112
1. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
2. Claim 2 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification does not disclose the conductive barrier structure is floating or is configurable to be biased at a voltage level higher than a lower one of voltage levels of a source and a drain of the semiconductor device as recited in claim 2.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 4, 14, 29 - 32 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Curatola et al. (2019/0280093).
With regard to claim 1, Curatola et al. disclose a semiconductor device (for example, figure 2) comprising:
a substrate (116) of a first semiconductor material (for example, paragraph [0023]);
a conductive barrier structure (a conductive barrier layer 104 functioning as a conductive barrier structure) on the substrate (116) and configurable to form a conductive channel (a charge carrier gas 112 or 113 functions as a conductive channel) therein and provide electrical isolation (the region 114 made of AlN or electrical insulators in order to provide electrical isolation; for example, see paragraphs [0023], [0024]) from the substrate (116).
a channel layer (106) of a second semiconductor material on the conductive barrier structure (104);
a barrier layer (108) on the channel layer (106), in which the channel layer (106) is between the barrier layer (108) and the conductive barrier structure (104); and a
gate (126) over the barrier layer (108) opposing the channel layer (106).
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The applicant’s claim 1 does not distinguish over the Curatola et al. reference regardless of the functions allegedly performed by the claimed device, because only the device per se is relevant, not the recited function of the conductive barrier structure configurable to form a conductive channel therein in an off state of the semiconductor device. In reference to the claim language referring to the function of the conductive barrier structure, intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. In re Casey,152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963).
Note that functional language in a device claim is directed to the device per se, no matter which of the device’s functions is referred to in the claim. See In re Ludtke and Sloan, 169 USPQ 563 at 567, and In re Swinehart, 169 USPQ 226, both of which make it clear that it is the patentability of the device per se which must be determined in a “functional language” claim and not the patentability of the function, and that an old or obvious device alleged to perform a new function is not patentable as a device, whether claimed in “functional language” terms or not. Note that the above case law makes clear that in such cases applicant has the burden of showing that a prior art device that appears reasonably capable of performing the allegedly novel function is in fact incapable of doing so. See MPEP § 2114. See also In re Schreiber, 44 USPQ2d 1429, 1432 (Fed. Cir. 1997) (Claim to a spout having “taper … such as to by itself jam up the popped popcorn before the end of the cone and permit the dispensing of only a few kernels at a shake,” anticipated by an oil can spout having the same shape as spout Applicant disclosed as being adapted for dispensing said only a few kernels) and In re King, 231 USPQ 136 (Fed. Cir, 1986) ("It did not suffice merely to assert that [the cited prior art] does not inherently achieve [the claimed function], challenging the PTO to prove the contrary by experiment or otherwise. The PTO is not equipped to perform such tasks") for discussions of the roles of examiner and applicant in determining when and how functional limitations distinguish a claim from prior art disclosing the same structure.
With regard to claim 2, Curatola et al. disclose the channel layer (106) is inherently configured to conduct a charge of a first polarity; and the conductive barrier structure (104) is inherently configured to conduct a charge of a second polarity opposite from the first polarity (for example, paragraph [0059] discloses GaN may be combined with AlGaN or InGaN to form an electron gas inversion region as the channel. The semiconductor device 100 may have AlInN/AlN/GaN barrier/spacer/channel layer structures. In general, the normally-off compound semiconductor transistor can be realized using any suitable III-nitride technology such as GaN that permits the formation of opposite polarity inversion regions due to piezoelectric effects); wherein the conductive barrier structure (104) having two-dimensional hole gas is floating (for example, see paragraph [0019]).
With regard to claim 3, Curatola et al. disclose the conductive barrier structure (104) includes an Aluminum Gallium Nitride (AlGaN) layer (for example, paragraphs [0024], [0059]).
With regard to claim 4, Curatola et al. disclose the first semiconductor material includes silicon, and the second semiconductor material includes Gallium Nitride (for example, see paragraph [0023]).
With regard to claim 14, Curatola et al. disclose a gate structure (126) comprising a first gate (referred to as “126A” by examiner’s annotation shown in fig. 2 below; wherein the gate portion 126A functioning a first gate) and a second gate (referred to as “126B” by examiner’s annotation shown in fig. 2 below; wherein the gate portion 126B functioning a second gate) over the barrier layer (108) opposing the channel layer (106); and a first electrical contact (referred to as “132A” by examiner’s annotation shown in fig. 2 below; wherein the first electrical contact 132A is a portion of the electrical contact 132) on a surface of the barrier layer (108) and a second electrical contact (118) on the surface of the barrier layer (108), the first gate (126A) is on a region in the channel layer (106).
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With regard to claim 29, Curatola et al. disclose a semiconductor device (for example, figure 1 or 2) comprising:
a substrate (116) of a first semiconductor material (for example, paragraph [0023]);
a conductive barrier structure (a conductive barrier layer 104 functioning as a conductive barrier structure) on the substrate (116) and configurable to form a conductive channel (a charge carrier gas 112 or 113 functions as a conductive channel) therein and provide electrical isolation (the region 114 made of AlN or electrical insulators in order to provide electrical isolation; for example, see paragraphs [0023], [0024]) from the substrate (116);
a channel layer (106) of a second semiconductor material on the conductive barrier structure (104);
a barrier layer (108) on the channel layer (106), in which the channel layer (106) is between the barrier layer (108) and the conductive barrier structure (104); and a
gate (126) over the barrier layer (108) opposing the channel layer (106);
a gate structure (126) comprising a first gate (referred to as “126A” by examiner’s annotation shown in fig. 2 below; wherein the gate portion 126A functioning a first gate) and a second gate (referred to as “126B” by examiner’s annotation shown in fig. 1 below; wherein the gate portion 126B functioning a second gate) over the barrier layer (108) opposing the channel layer (106); and a first electrical contact (referred to as “132A” by examiner’s annotation shown in fig. 2 below; wherein the first electrical contact 132A is a portion of the electrical contact 132) and a second electrical contact (118) on a surface of the barrier layer (108), in which the first gate (126A) and the second gate (126B) are between the first electrical contact (132A) and the second electrical contact (118).
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The applicant’s claim 29 does not distinguish over the Curatola et al. reference regardless of the functions allegedly performed by the claimed device, because only the device per se is relevant, not the recited function of the conductive barrier structure configurable to form a conductive channel therein in an off state of the semiconductor device. In reference to the claim language referring to the function of the conductive barrier structure, intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. In re Casey,152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963).
Note that functional language in a device claim is directed to the device per se, no matter which of the device’s functions is referred to in the claim. See In re Ludtke and Sloan, 169 USPQ 563 at 567, and In re Swinehart, 169 USPQ 226, both of which make it clear that it is the patentability of the device per se which must be determined in a “functional language” claim and not the patentability of the function, and that an old or obvious device alleged to perform a new function is not patentable as a device, whether claimed in “functional language” terms or not. Note that the above case law makes clear that in such cases applicant has the burden of showing that a prior art device that appears reasonably capable of performing the allegedly novel function is in fact incapable of doing so. See MPEP § 2114. See also In re Schreiber, 44 USPQ2d 1429, 1432 (Fed. Cir. 1997) (Claim to a spout having “taper … such as to by itself jam up the popped popcorn before the end of the cone and permit the dispensing of only a few kernels at a shake,” anticipated by an oil can spout having the same shape as spout Applicant disclosed as being adapted for dispensing said only a few kernels) and In re King, 231 USPQ 136 (Fed. Cir, 1986) ("It did not suffice merely to assert that [the cited prior art] does not inherently achieve [the claimed function], challenging the PTO to prove the contrary by experiment or otherwise. The PTO is not equipped to perform such tasks") for discussions of the roles of examiner and applicant in determining when and how functional limitations distinguish a claim from prior art disclosing the same structure.
With regard to claim 30, Curatola et al. disclose the first semiconductor material includes silicon, and the second semiconductor material includes Gallium Nitride (for example, see paragraph [0023]).
With regard to claim 31, Curatola et al. disclose the channel layer (106) is inherently configured to conduct a charge of a first polarity; and the conductive barrier structure (104) is inherently configured to conduct a charge of a second polarity opposite from the first polarity (for example, paragraph [0059] discloses GaN may be combined with AlGaN or InGaN to form an electron gas inversion region as the channel. The semiconductor device 100 may have AlInN/AlN/GaN barrier/spacer/channel layer structures. In general, the normally-off compound semiconductor transistor can be realized using any suitable III-nitride technology such as GaN that permits the formation of opposite polarity inversion regions due to piezoelectric effects);
With regard to claim 32, Curatola et al. disclose a conductive structure (112) electrically coupled between the conductive barrier structure (104) and the channel layer (106).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 - 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Curatola et al. (20190280093) in view of Kushida et al. (10680091).
With regard to claim 6, Curatola et al. do not clearly disclose the conductive barrier structure includes a quantum well configured to confine a first charge having an opposite polarity from a second charge that the channel layer is configured to conduct.
However, Kushida et al. discloses the conductive barrier structure (21, 22) includes a quantum well (22) configured to confine a first charge having an opposite polarity (p-type) from a second charge (i-type) that the channel layer (24) is configured to conduct. (for example, see fig. 7).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Curatola et al.’s device to have the conductive barrier structure includes a quantum well configured to confine a first charge having an opposite polarity from a second charge that the channel layer is configured to conduct as taught by Kushida et al. in order to enhance the strength of electric field between the drain portion and the source portion for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claims 7 - 9, Curatola et al. do not clearly disclose an electrical contact that penetrates through the barrier layer; wherein: the electrical contact is a first electrical contact; the semiconductor device further comprises a second electrical contact; the gate and the second electrical contact are on a region in the channel layer; and the first electrical contact is outside the region wherein: the electrical contact is a first electrical contact; the semiconductor device further comprises a second electrical contact and a third electrical contact on two sides of the gate; and the first electrical contact is electrically coupled to the gate.
However, Kushida et al. discloses an electrical contact (102) that penetrates through the barrier layer (21); wherein: the electrical contact (102) is a first electrical contact; the semiconductor device further comprises a second electrical contact (104); the gate (103) and the second electrical contact (104) are on a region in the channel layer (24); and the first electrical contact (102) is outside the region; or wherein: the electrical contact (102) is a first electrical contact; the semiconductor device further comprises second and third electrical contacts (104) on two sides of the gate (103); and the first electrical contact (102) is electrically coupled (couple via channel layer 24) to the gate (103).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Curatola et al.’s device to have an electrical contact that penetrates through the barrier layer; wherein: the electrical contact is a first electrical contact; the semiconductor device further comprises a second electrical contact; the gate and the second electrical contact are on a region in the channel layer; and the first electrical contact is outside the region wherein: the electrical contact is a first electrical contact; the semiconductor device further comprises a second electrical contact and a third electrical contact on two sides of the gate; and the first electrical contact is electrically coupled to the gate as taught by Kushida et al. in order to enhance the electrical connection efficiency between the drain portion and the source portion, as is known to one of ordinary skill in the art.
Allowable Subject Matter
7. Claims 5, 10 – 13, 15, 16, 33 - 36 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 5, 10 – 13, 15, 16, 33 - 36 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as the conductive barrier structure includes: a first confinement layer; a second confinement layer; and a third layer between the first confinement layer and the second confinement layer; the third layer has a lower band gap energy than each of the first confinement layer and the second confinement layer; and the semiconductor device further includes a conductive structure that penetrates through at least one of the first confinement layer or the second confinement layer as recited in claim 5, an isolation structure between respective first portions of the barrier layer, the channel layer, and the conductive barrier structure and respective second portions of the barrier layer, the channel layer, and the conductive barrier structure, wherein the gate is a first gate over the first portion of the barrier layer; and a second gate over the second portion of the barrier layer as recited in claim 10, a first driver circuit having a first driver output and a second driver output, the first driver output electrically coupled to the first electrical contact, and the second driver output electrically coupled to the first gate; and a second driver circuit having a third driver output and a fourth driver output, the third driver output electrically coupled to the second electrical contact, and the fourth driver output electrically coupled to the second gate as recited in claim 15, a first isolation structure between respective first portions of the barrier layer and the channel layer and respective second portions of the barrier layer and the channel layer, wherein the gate is a first gate on the first portion of the barrier layer; a second isolation structure between the respective first portions of the barrier layer and the channel layer and respective third portions of the barrier layer and the channel layer; a first conductive structure electrically coupled between the second portion of the channel layer and the second portion of the conductive barrier structure; a second gate on the first portion of the barrier layer; a first electrical contact and a second electrical contact on the first portion of the barrier layer; a third electrical contact electrically coupled to the first conductive structure; a second conductive structure electrically coupled between the third portion of the channel layer and the third portion of the conductive barrier structure; and a fourth electrical contact electrically coupled to the second conductive structure as recited in claim 16, a first isolation structure between respective first portions of the barrier layer and the channel layer and respective second portions of the barrier layer and the channel layer; a second isolation structure between the respective first portion of the barrier layer and the channel layer and respective third portions of the barrier layer and the channel layer;
wherein: the first gate and the second gate are on the first portion of the barrier layer; the first electrical contact and the second electrical contact are on the first portion of the barrier layer as recited in claim 33, and a first driver circuit having a first driver output and a second driver output, the first driver output being electrically coupled to the first electrical contact, and the second driver output being electrically coupled to the first gate; and a second driver circuit having a third driver output and a fourth driver output, the third driver output being electrically coupled to the second electrical contact, and the fourth driver output being electrically coupled to the second gate as recited in claim 36.
Claims 17 – 28 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as an isolation structure between respective first portions of the barrier layer, the channel layer, and the conductive barrier structure and respective second portions of the barrier layer, the channel layer, and the conductive barrier structure; a first gate over the first portion of the barrier layer opposing the channel layer;
a first electrical contact on a surface of the first portion of the barrier layer opposing the channel layer; a second gate over the second portion of the barrier layer opposing the channel layer; and a second electrical contact on a surface of the second portion of the barrier layer opposing the channel layer, in which the second electrical contact is electrically coupled to the first electrical contact as recited in claim 17.
Response to Amendment
8. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
9. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
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