DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hatem et al. (US Patent No. 9,589,802).
[Re claim 15] Hatem discloses the system, comprising: one or more process chamber operable to: deposition chamber (510); etching chamber (506); and an ion processing tool (508) within the one or more chambers (see figure 5 and column 9 line 7-64). The limitation “form a gate-all-around (GAA) stack comprising a plurality of alternating first layers and second layers, wherein the GAA stack is positioned atop a bottom dielectric isolation (BDI) layer; form a source/drain (S/D) cavity by etching the plurality of alternating first layers and second layers; and form an inner spacer in the S/D cavity, adjacent the plurality of alternating first layers and second layers; and an ion processing, wherein the ion processing to perform an implant by directing ions to the GAA stack, through the S/D cavity, wherein the implant is performed at a temperature greater than 5000 Celsius, and wherein a S/D material is formed in the S/D cavity following the implant” are limitations directed to details of the device being made by the claimed apparatus, and therefore do not impart significant patentable weight. See MPEP 2114(II).
[Re claim 16] Hatem discloses the system wherein the ion processing tool (508) (see column 9 lines 33-48). The limitation “operable to direct the ions into the inner spacer and into the first layers of the plurality of alternating first layers and second layers” are limitations directed to details of the device being made by the claimed apparatus, and therefore do not impart significant patentable weight. See MPEP 2114(II).
[Re claim 17] Hatem discloses the system wherein the ion processing tool is beamline tool (508) (see column 9 lines 33-48). The limitation “operable to direct the ions into the GAA stack at a non-zero angle relative to a plane defined by a sidewall surface of the inner spacer, and wherein the ions are boron ions” are limitations directed to details of the device being made by the claimed apparatus, and therefore do not impart significant patentable weight. See MPEP 2114(II).
[Re claim 18] Hatem discloses the system wherein the ion processing tool is a plasma doping tool operable to perform a plasma doping process (508) (see column 9 lines 33-48).
[Re claim 19] Hatem discloses the system wherein the ion processing tool (508) (see column 9 lines 49-64). The limitation “operable to direct the ions to the GAA stack before or after formation of the BDI layer” are limitations directed to details of the device being made by the claimed apparatus, and therefore do not impart significant patentable weight. See MPEP 2114(II).
[Re claim 20] Hatem discloses the system comprising deposition chamber (510) operable to form one or more of silicon oxide, silicon nitride, silicon carbide, or a high-k material (see column 9 lines 49-64). The limitation “the BDI layer comprises one or more of silicon oxide, silicon nitride, silicon carbide, or a high-k material” are limitations directed to details of the device being made by the claimed apparatus, and therefore do not impart significant patentable weight. See MPEP 2114(II).
Allowable Subject Matter
Claim 1-14 are allowed.
The following is an examiner's statement of reasons for allowance: Claim 1 allowable because of the closest prior art (US Patent No 9,923,055) discloses the method of forming a gate-all-around (GAA) stack comprising a plurality of alternating first layers and second layers (106), wherein the GAA stack is positioned atop a bottom dielectric isolation (BDI) layer; forming a source/drain (S/D) cavity by etching the plurality of alternating first layers and second layers; forming an inner spacer (702/1102) in the S/D cavity, adjacent the plurality of alternating first layers and second layers; forming a S/D material (1202) in the S/D cavity and implanting the S/D material after forming the S/D material (see figure 1A-12 and column 7 line 53 through column 11 line 43). However, the closest prior art, either singly or in combination, fails to anticipate or render obvious, the method, the step of performing an implant by directing ions to the GAA stack, through the S/D cavity, wherein the implant is performed at a temperature greater than 500° Celsius; and forming a S/D material in the S/D cavity following the implant. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
The following is an examiner's statement of reasons for allowance: Claim 8 allowable because of the closest prior art (US Patent No 10,825,904) discloses the method of forming a gate-all-around (GAA) device, comprising: forming a nanowire stack atop a bottom dielectric isolation (BDI) layer, the nanowire stack comprising: a plurality of alternating first layers and second layers; and an outer gate spacer adjacent the plurality of alternating first layers and second layers; forming a source/drain (S/D) cavity by etching the plurality of alternating first layers and second layers, and by etching an outer gate spacer located adjacent the nanowire stack; forming an inner spacer in the S/D cavity, adjacent the plurality of alternating first layers and second layers (see figure 1A-12 and column 7 line 53 through column 11 line 43). However, the closest prior art, either singly or in combination, fails to anticipate or render obvious, the method, the step of performing an implant by directing ions to the inner spacer, through the S/D cavity, wherein the implant is performed at a temperature greater than 500° Celsius; and forming a S/D material in the S/D cavity following the implant. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 2-7 and 8-14 depend from claim 1 or 8 so they are allowable for the same reason.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Cheng et al. (US Patent No. 9,923,055).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYOUNG LEE whose telephone number is (571)272-1982. The examiner can normally be reached M to F, 10am to 6pm.
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/KYOUNG LEE/ Primary Examiner, Art Unit 2817