DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed December 8, 2023.
Claims 1-20 are pending. Claims 1, 16 and 20 are independent.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 received on February 27, 2025.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on December 8, 2023 and August 22, 2024. These IDSs have been considered.
Drawings
Figure 6 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
Applicant’s Figure 6 is identical to WO 2022/188010 Figure 8.
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 13-15 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by IM (U.S. 2023/0122541).
Regarding independent claim 1, IM discloses a memory device (Fig. 2A), comprising:
a substrate (Fig. 2A: 101);
a read word line on the substrate (Fig. 2A: 180);
a first channel electrically connected to the read word line and extending along a plane perpendicular to an upper surface of the substrate (Fig. 2A: 170);
a second channel facing the first channel in parallel (Fig. 2A: 120);
a first gate insulation layer adjacent to the first channel between the first channel and the second channel (Fig. 2A: 160);
a second gate insulation layer adjacent to the second channel between the first channel and the second channel (Fig. 2A: 130a and 130b);
a gate electrode adjacent to the first gate insulation layer between the first gate insulation layer and the second gate insulation layer (Fig. 2A: 150);
a write word line adjacent to the second gate insulation layer between the first gate insulation layer and the second gate insulation layer (Fig. 2A: 140a and 140b);
a read bit line electrically connected to the first channel (Fig. 2A: 190); and
a write bit line electrically connected to the second channel (Fig. 2A: 110).
Regarding claim 2, IM discloses wherein the first channel, the second channel, the first gate insulation layer, the second gate insulation layer, the gate electrode, and the write word line have a shape protruding in a direction perpendicular to the upper surface of the substrate (Fig. 2A shows a plurality of elements over the substrate 101 having a shape protruding in a direction perpendicular to the upper surface of the substrate).
Regarding claim 13, IM discloses a lower surface of the first channel contacts the read word line, and an upper surface of the first channel contacts the read bit line (Fig. 2A: first channel 170 electrically contacts the read word line 180 and the read bit line 190 through contacts 116 and 118).
Regarding claim 14, IM discloses the first channel, the first gate insulation layer, and the gate electrode collectively define a read transistor (Fig. 2A: RST), and
the second channel, the second gate insulation layer, and the write word line collectively define a write transistor (Fig. 2A: WTS).
Regarding claim 15, IM discloses wherein the first channel and the second channel each comprises an oxide semiconductor material (see page 4, par. 0048 and page 5, par. 0065), and
the read transistor and the write transistor each include a separate oxide semiconductor transistor (Fig. 2A: RTS and WTS).
Regarding independent claim 20, IM discloses an electronic device (Fig. 5) comprising:
a memory device (Fig. 2A); and
a memory controller configured to control the memory device to read data from the memory device or write data to the memory device (see page , par. 0073),
wherein the memory device includes
a substrate (Fig. 2A: 101),
a read word line on the substrate (Fig. 2A: 180),
a first channel electrically connected to the read word line and extending along a plane perpendicular to an upper surface of the substrate (Fig. 2A: 170),
a second channel facing the first channel in parallel (Fig. 2A: 120),
a first gate insulation layer adjacent to the first channel between the first channel and the second channel (Fig. 2A: 160),
a second gate insulation layer adjacent to the second channel between the first channel and the second channel (Fig. 2A: 130a and 130b),
a gate electrode adjacent to the first gate insulation layer between the first gate insulation layer and the second gate insulation layer (Fig. 2A: 150),
a write word line adjacent to the second gate insulation layer between the first gate insulation layer and the second gate insulation layer (Fig. 2A: 140a and 140b),
a read bit line electrically connected to the first channel (Fig. 2A: 190), and
a write bit line electrically connected to the second channel (Fig. 2A: 110).
Claims 16 and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (WO 2022/188010; hereinafter “Huang”).
Regarding independent claim 16, Huang discloses a memory device (Fig. 8), comprising:
a plurality of memory cells (Fig. 8) extending two-dimensionally in a plurality of rows and a plurality of columns (Fig. 8 shows memory cells arranged in rows and columns);
a plurality of read word lines extending along a first direction and connected to separate, respective columns of memory cells of the plurality of memory cells (Fig. 8: RWLs);
a plurality of read bit lines extending along a second direction perpendicular to the first direction and connected to separate, respective rows of memory cells of the plurality of memory cells (Fig. 8: RBLs);
a plurality of write word lines extending along the second direction and connected to separate, respective rows of memory cells of the plurality of memory cells (Fig. 8: WWLs); and
a plurality of write bit lines extending along the second direction and connected to separate, respective rows of memory cells of the plurality of memory cells (Fig. 8: WBLs),
wherein each memory cell of the plurality of memory cells includes
a substrate (Fig. 12(a): 100),
a first channel extending along a plane perpendicular to an upper surface of the substrate (see Fig. 12(b): the black line with double arrows represents that the channel is a “vertical” channel perpendicular to the substrate 100),
a second channel facing the first channel in parallel (Fig. 19 shows a plurality of channel facing each other in parallel),
a first gate insulation layer adjacent to the first channel between the first channel and the second channel (Fig. 12(a): 5),
a second gate insulation layer adjacent to the second channel between the first channel and the second channel (Fig. 12(a): 5), and
a gate electrode adjacent to the first gate insulation layer between the first gate insulation layer and the second gate insulation layer (Fig. 12(a): 1).
Regarding claim 18, Huang discloses wherein the first channel is electrically connected to one read word line of the plurality of read word lines and one read bit line of the plurality of read bit lines (Fig. 26 shows RWL(WBL) is electrically connected to the memory cells comprising a first channel),
the second channel is electrically connected to one write bit line of the plurality of write bit lines (Fig. 23 shows WBL 94 electrically connected to second channel of memory cells), and
one of the plurality of write word lines is adjacent to the second gate insulation layer between the first gate insulation layer and the second gate insulation layer (Fig. 26: WWL).
Regarding claim 19, Huang discloses wherein the plurality of memory cells includes a first memory cell and a second memory cell adjacent to each other in the first direction, wherein the first memory cell and the second memory cell have a mirror symmetry across a plane of symmetry that extends perpendicular to the first direction (Fig. 24 shows a plurality of memory cells having a mirror symmetry).
Allowable Subject Matter
Claims 3-12 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to independent claim 3, there is no teaching or suggestion in the prior art of record to provide the recited read word line is on the substrate such that a lower surface and opposite side surfaces of the read word line are surrounded by the substrate, the read word line extending in a first direction parallel to the upper surface of the substrate.
With respect to independent claim 5, there is no teaching or suggestion in the prior art of record to provide the recited first gate insulation layer comprises a main body portion extending in a direction perpendicular to the upper surface of the substrate, and an extension portion extending from a lower portion of the main body portion of the first gate insulation layer in a separate direction parallel to the upper surface of the substrate.
With respect to independent claim 17, there is no teaching or suggestion in the prior art of record to provide the recited each read word line of the plurality of read word lines is on the substrate such that a lower surface and opposite side surfaces of the read word line are surrounded by the substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825