DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Non-Final office action based on application 18/534,294 filed December 8, 2023. Claims 1-20 are currently pending and have been considered below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 & 6 is/are rejected under 35 U.S.C. 102(a) as being anticipated by Shintaro (Japanese Publication 2012227379).
Regarding claim 1, Shintaro disclose a bonding pad of an integrated circuit comprising:
a surface electrode layer (Fig.1, 103a & 103b) having a first surface;
a resistance layer (108) having a second surface disposed at an interval from the first surface in a first direction orthogonal to the first surface, the second surface facing a side opposite to the first surface;
a stress buffer layer (101a-c) disposed between the surface electrode layer and the resistance layer in the first direction; and
a connecting member (102 & 108) connecting the surface electrode layer and the stress buffer layer in the first direction and being in contact with each of the surface electrode layer and the stress buffer layer, wherein the stress buffer layer extends over the entire bonding pad in a direction orthogonal to the first direction, the connecting member includes an insulator (108) that is in contact with the each of the surface electrode layer and the stress buffer layer in the first direction, and at least one plug (102) that is in contact with the insulator in the direction orthogonal to the first direction and electrically connect the surface electrode layer and the stress buffer layer, and
a thickness of the stress buffer layer (101b) can be about 450nm in the first direction and can be larger than a thickness of the surface electrode layer (103c & 103b) which can be about 370nm in the first direction (Paragraph [0031]).
Regarding claim 6, Shintaro further discloses:
the at least one plug (102) includes a plurality of plugs disposed at intervals between each other in the direction orthogonal to the first direction, and the insulator (108) is embedded between the plurality of the plugs.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shintaro (Japanese Publication 2012227379) in view of Yamazaki (US Patent 7,863,705).
Regarding claim 7, Shinatro discloses all of the limitations of claim 1 (addressed above). Shintaro does not disclose the first surface includes a first region to which a conductive member constituting a part of the integrated circuit device is bonded, and a second region located outside the first region, the connecting member includes a third region overlapping with the first region in the first direction, and a fourth region overlapping with the second region in the first direction, the at least one plug is disposed only in the fourth region of the connecting member, and the third region of the connecting member includes the insulator. However Yamakazi disclose a bond pd structure comprising:
A surface electrode (Fig. 1a/1b, 16) having a first surface with an opening (17a) for a bonding wire forming a first region and a second region beyond the opening, a stress buffer layer (12a), and connecting member with a plug (15)/insulator (13) between the surface electrode and stress buffer layer including a third region overlapping the with the first region in the first direction and a fourth region overlapping with the second region in the first direction, wherein the at least one plug (15) is disposed only in the fourth region of the connecting member, and the third region of the connecting member includes the insulator (13).
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It would have been obvious to those having ordinary skill in the art at the time of invention to form the connecting member including an insulator in the third region and plug only in the fourth region because it will serve to prevent cracks within the insulator from growing toward a position outside the plugs and forms a barrier against ingress of water (Col. 4, Lines 15-25).
Claim(s) 9 & 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shintaro (Japanese Publication 2012227379) in view of Wang (Pre-Grant Publication 2006/0226547).
Regarding claim 9 & 10, Shintaro further discloses:
An integrated circuit element including the bonding pad according to claim 1, wherein a conductive member (105) is bonded by ultrasonic waves/load (Paragraph [0045]).
Shintaro does not discloses an interlayer insulating film bonded to the second surface of the bonding pad. However Wang discloses a bonding pad structure comprising:
A surface electrode (Fig. 1, 101) having first surface, a stress buffer layer (103), a plug (102a-b), an insulator (222), and a resistance layer (220/218) having a second surface, wherein an interlayer insulating layer (216/214) is bonded to the second surface.
It would have been obvious to those having ordinary skill in the art at the time of invention to form the interlayer insulating layer bonded to the second surface because it can provide insolation between different metallizations formed throughout the semiconductor device.
Allowable Subject Matter
Claims 2-5, 8, & 11-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 2 is considered allowable because none of the prior art either alone or in combination discloses the stress buffer layer includes a first metal layer and a second metal layer laminated on each other in the first direction, the first metal layer is in contact with the connecting member, the second metal layer is in contact with the resistance layer, each of the first metal layer and the second metal layer extends over the entire bonding pad in the direction orthogonal to the first direction, and a Young's modulus of a first metal material constituting the first metal layer is lower than a Young's modulus of a second metal material constituting the second metal layer, and lower than a Young's modulus of a material constituting the at least one plug. Claims 3-4 & 11-20 are also allowable based on their dependency from claim 2.
Claim 5 is considered allowable because none of the prior art either alone or in combination discloses the stress buffer layer includes a metal layer and an insulating layer laminated on each other in the first direction, the metal layer is in contact with the surface electrode layer, the insulating layer is in contact with the resistance layer, each of the metal layer and the insulating layer extends over the entire bonding pad in the direction orthogonal to the first direction, and a rigidity modulus of a material constituting the insulating layer is lower than a rigidity modulus of a material constituting the at least one plug.
Claim 8 is considered allowable because none of the prior art either alone or in combination discloses the thickness of the stress buffer layer in the first direction is greater than or equal to a total value of a thickness of the surface electrode layer in the first direction and a thickness of the connecting member in the first direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
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/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818