DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is response to Application 18/534,390 filed on 12/08/2023. Claims 1-20 are pending in the office action.
Claim Objections
Claims 1, 15, 18, and 20 are objected to because of the following informalities:
As per claim 1:
line 4, replaces “according to a distance” with -- of a saturation current (IDSat) of a transistor as a function of --.
line 6, after “within” inserts -- determined --.
As per claim 15:
line 4, replaces “a through-via” with -- the through-via --.
line 6, replaces “according to” with -- of a saturation current (IDSat) of a transistor as a function of --.
line 8, after “within” inserts -- determined --.
As per claim 18:
line 8, replaces “according to” with -- of a saturation current (IDSat) of a transistor as a function of --.
line 10, after “within” inserts -- determined --.
As per claim 20: line 2, replaces “a first cell” with -- the first cell --.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 1: the limitation "the distance from the through-via to the first cell", in the last limitation, different from “a distance from the through-via” in line 3. There is insufficient antecedent basis for this limitation in the claim.
Also recited “a first cell of the plurality of standard cells is placed within the keep-out zone” which is unclear that “the keep-out zone”
recited the limitation “setting a timing margin based on the distance from the through-via to the first cell” that is unclear how can “a timing margin” to be set? And also unclear “setting a timing margin for entire semiconductor chip, a plurality of standard cells, or the first cell?” because the entire of claim language/limitation does not give any information to calculate/determine any “delay/slack/timing” or particular element. Hence, one of ordinary skills in the art would not be able to practice the claimed invention.
As per claims 15 and 18: are also rejected similar as per claim 1.
As per claims 15 and 18: also recited “a semiconductor chip” and “an integrated circuit” which is unclear their relationship.
As per claims 2-14, 16-17, and 19-20 are also rejected because are depended directly or indirectly from claims 1, 15, and 18, respectively.
Prior Arts
Hsieh et al., (U.S. Pat. 8,604,619)
Hsieh discloses Keep out zones (KOZ) are formed for a through silicon via (TSV), to determine KOZ comprises only those areas where the stress impact to a performance metric is larger than or equal to the performance threshold used to determining the KOZ. A point is not in the KOZ if the stress impact to the performance metric in the point is not as big as the performance threshold, no matter how close the point is to the center of the TSV. For example, the area 13 in FIG. 1(b) has a stress impact in the range of -10% to -20%, and the area 17 has a stress impact in the range of 10% to 20%. If a performance threshold 10% is used to determine the KOZ, then both areas 13 and 17 are in the KOZ. On the other hand, a much larger area such as area 11 and 12 has stress impact less than the performance threshold 10% which determines the KOZ for the TSV. Therefore the area 11 in the [010] direction but within the circle 101 is not a KOZ and devices can be placed in this area (see fig. 1a-1d, col. 3, ll. 45-60).
Kim et al., (U.S. Pub. 20220130841)
Kim discloses semiconductor elements (e.g., a resistance element or a power storage element) that are relatively less sensitive to changes in electrical characteristics due to deterioration of the TSV are disposed in an area of the keep-out zone KOZ from a point spaced apart from the TSV by a predetermined distance DIST to a circuit block.
Hu et al., (U.S. Pat. 11,080,455).
Hu discloses a TSV structure in an IC should be provided within the boundaries of an STI structure, the boundary defining a region where no device should be disposed. The TSV structure should also be further surrounded by a KOZ region wherein only dummy devices may be placed. By providing all the dummy active regions 208 within the first layout region (i.e. KOZ) with substantially identical dimension in the A-direction, the uniformity in the KOZ increased, resulting in a reduction in non-uniform loading effect on the active devices during the manufacturing process of the IC. As a result, the performance of the active devices may be improved. In some embodiments, the saturation current of the active devices having dummy devices in the KOZ with dummy active regions having substantially identical dimension in the A-direction may increase by about 3% to about 20%, and threshold voltage value of the active devices having dummy devices in the KOZ with dummy active regions having substantially identical dimension in the A-direction may decrease by about 3% to about 20%, when compared to active devices in IC that has dummy devices with dummy active regions that has different dimensions in the A-direction and B-direction. In other words, by providing dummy active regions 208 in the first layout region with substantially identical dimension in the A-direction, the speed of active devices improves.
Conclusion
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NGHIA M. DOAN
Primary Examiner
Art Unit 2851
/NGHIA M DOAN/Primary Examiner, Art Unit 2851
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