DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10 are pending in the application.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file (JP2021-097420 Japan 06/10/2021).
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 12/08/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 12/08/2023. These drawings are review and accepted by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 10 is objected to under 37 CFR 1.75(c) as being in improper dependent form for failing to further limit the subject matter of a previous claim. Applicant is required to cancel the claim(s), or amend the claim(s) to place the claim(s) in proper dependent form, or rewrite the claim(s) in independent claim.
Claim 10 recasts the claimed invention by changing the preamble to “A voltage application method of applying an external supply voltage to the external terminal provided in the semiconductor device.” Claim 10, however, is drafted to depend from claim 1, which is direct to “a semiconductor device”. This claim is technically treatable as independent claims; however, to promote clarity at time of claim fee calculations, it is recommended to redraft these claims in actual independent form.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Kodama et al (US 8,890,503 B2 hereinafter “Kodama”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Kodama, for example in Figs. 1-9, discloses a semiconductor device (see for example in Fig. 2 related in Figs. 1, 3-9), comprising: an internal power supply (e.g., 104 and 105; in Figs. 1-2 related in Figs. 3-9) configured to generate an internal supply voltage (e.g., VDD2; in Fig. 2 related in Figs. 1, 3-9) from an input voltage (e.g., VDD1; in Fig. 2 related in Figs. 1, 3-9); a first circuit block configured to operate (e.g., block 113; in Fig. 2 related in Figs. 1, 3-9) by being supplied with the internal supply voltage (e.g., VDD2; in Fig. 2 related in Figs. 1, 3-9); a second circuit block configured to operate (e.g., blocks 107 and 108; in Fig. 2 related in Figs. 1, 3-9) by being supplied with a node voltage (e.g., Vtap; in Fig. 2 related in Figs. 1, 3-9) appearing at an internal node (e.g., Nn; in Fig. 2 related in Figs. 1, 3-9); and a switcher configured to switch a connection destination of the internal node (e.g., switch 106; in Fig. 2 related in Figs. 1, 3-9), wherein the switcher includes: a first switch connected between an application terminal for the internal supply voltage and the internal node (e.g., SW1-SWn; in Fig. 2 related in Figs. 1, 3-9); and a second switch (e.g., 112; in Fig. 2 related in Figs. 1, 3-9) connected between an external terminal (e.g., VDD1; in Fig. 2 related in Figs. 1, 3-9) and the internal node (e.g., Vtap; in Fig. 2 related in Figs. 1, 3-9), the second circuit block includes a switch controller (e.g., block 108; in Fig. 2 related in Figs. 1, 3-9) configured to control the first and second switches individually (via CNTRL1 and CNTR1; in Fig. 2 related in Figs. 1,3-9), the switch controller controls the switcher such that switching of an operating state of the switcher between a first state where the first switch is on and the second switch is off and a second state where the first switch is off and the second switch is on proceeds via a third state where the first and second switches are both on (see for example in Figs. 2-3, 8-9 related in Figs. 1, 4-7).
For apparatus claims 1-9, MPEP 2112.01(I) instructs examiners, “When the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed inherent.” Kodama et al. disclose a substantially identical semiconductor device; the recited functions are presumed inherent. See also, MPEP Foreword (“[T]he Manual contains instructions to examiners, as well as other material in the nature of information and interpretation, and outlines the current procedures which the examiners are required or authorized to follow in appropriate cases in the normal examination of a patent application.”).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device does not possess the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicants are reminded that argument of counsel is not evidence (see MPEP 2145(I)). Applicants are reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 2, Kodama, for example in Figs. 1-9, discloses wherein the internal power supply only has a capacity to feed a current to the application terminal for the internal power supply (see for example in Figs. 2-3, 8-9 related in Figs. 1, 4-7, as discussed above).
Regarding claim 3, Kodama, for example in Figs. 1-9, discloses wherein the second circuit block includes a load circuit that requires different driving voltages in different operating modes (see for example in Figs. 2-3, 8-9 related in Figs. 1, 4-7, as discussed above).
Regarding claim 4, Kodama, for example in Figs. 1-9, discloses wherein the load circuit is a memory that requires different driving voltages during a data writing period and during a data non-writing period (see for example in Figs. 2-3, 8-9 related in Figs. 1, 4-7, as discussed above), and the switch controller keeps the switcher in the first state during the data non-writing period and in the second state during the data writing period (see for example in Figs. 2-3, 8-9 related in Figs. 1, 4-7, as discussed above).
Regarding claim 5, Kodama, for example in Figs. 1-9, discloses wherein the second circuit block is a digital circuit block that is a target on which to execute quiescent supply current testing (see for example in Figs. 2-3, 8-9 related in Figs. 1, 4-7, as discussed above), and the switch controller keeps the switcher in the first state during a non-execution period of the quiescent supply current testing and in the second state during an execution period of the quiescent supply current testing (see for example in Figs. 2-3, 8-9 related in Figs. 1, 4-7, as discussed above).
Regarding claim 6, Kodama, for example in Figs. 1-9, discloses wherein the second switch is an N-channel MOSFET (see for example in Figs. 2-3, 8-9 related in Figs. 1, 4-7, as discussed above).
Regarding claim 7, Kodama, for example in Figs. 1-9, discloses further comprising a resistor for limiting a current passing from the external terminal to a third circuit block (see for example in Figs. 2-3, 8-9 related in Figs. 1, 4-7, as discussed above).
Regarding claim 8, Kodama, for example in Figs. 1-9, discloses further comprising a clamper for limiting a voltage applied from the external terminal to the third circuit block downstream of the resistor (see for example in Figs. 2-3, 8-9 related in Figs. 1, 4-7, as discussed above).
Regarding claim 9, Kodama, for example in Figs. 1-9, discloses wherein the semiconductor device is enabled and disabled according to an enable signal fed to the external terminal when the switcher is in the first state (see for example in Figs. 2-3, 8-9 related in Figs. 1, 4-7, as discussed above).
Regarding claim 10, Kodama, for example in Figs. 1-9, discloses a voltage application method of applying an external supply voltage to the external terminal provided in the semiconductor device (see for example in Figs. 2-3, 8-9 related in Figs. 1, 4-7, as discussed above) according to claim 1, the method comprising: a step of setting the external supply voltage to a first voltage equal to or higher than a target voltage of the internal supply voltage before a switch from the first state to the third state (see for example in Figs. 2-3, 8-9 related in Figs. 1, 4-7, as discussed above); a step of raising the external supply voltage from the first voltage to a second voltage after a switch from the third state to the second state (see for example in Figs. 2-3, 8-9 related in Figs. 1, 4-7, as discussed above); a step of dropping the external supply voltage from the second voltage to the first voltage before a switch from the second state to the third state (see for example in Figs. 2-3, 8-9 related in Figs. 1, 4-7, as discussed above); and a step of stopping application of the external supply voltage after the a switch from the second state to the third state (see for example in Figs. 2-3, 8-9 related in Figs. 1, 4-7, as discussed above).
For method claims 10, MPEP 2112.02(I) instructs examiners, “When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process.” Kodama et al.’s identical device is assumed to inherently perform the claimed process. see also, MPEP Foreword (“[T]he Manual contains instructions to examiners, as well as other material in the nature of information and interpretation, and outlines the current procedures which the examiners are required or authorized to follow in appropriate cases in the normal examination of a patent application.”).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device does not possess the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicants are reminded that argument of counsel is not evidence (see MPEP 2145(I)). Applicants are reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Applicant are reminded that when presenting amendments to claims. In order to be fully responsive, an attempt should be made to point out the patentable novelty (see MPEP 714.04). Additionally, Applicant should point out where and/or how the originally filed disclosure supports the amendment(s) (see MPEP 2163 (II)(A)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THA-O H BUI whose telephone number is (571)270-7357. The examiner can normally be reached M-F 7:00AM - 3:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALEXANDER SOFOCLEOUS can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THA-O H BUI/Primary Examiner, Art Unit 2825 09/16/2025