Prosecution Insights
Last updated: April 19, 2026
Application No. 18/534,714

DISPLAY DEVICE MANUFACTURING METHOD

Non-Final OA §102
Filed
Dec 11, 2023
Examiner
WINTERS, SEAN AYERS
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Magnolia White Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
3y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
97 granted / 112 resolved
+18.6% vs TC avg
Strong +25% interview lift
Without
With
+24.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
80 currently pending
Career history
192
Total Applications
across all art units

Statute-Specific Performance

§103
58.8%
+18.8% vs TC avg
§102
30.6%
-9.4% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 112 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement(s) (IDS) submitted on 12/11/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jung (U.S. PG Pub No US2024/0121989A1). Regarding claim 1, Jung teaches a display device manufacturing method [see figs. 6-15, 0116], comprising: forming a lower electrode (AE2) fig. 6 [0167]; forming a rib (IL1) fig. 12 [0169] covering at least a part (right sidewall) of the lower electrode (AE2); and forming a partition (P) (see annotated fig. 15 below) on the rib (IL1), the partition (P) including a conductive bottom portion (BNK) fig. 15 [0173], an insulating stem portion (comprising CLP1) fig. 15 [0129, 0139] located on the bottom portion (BNK), and a top portion (comprising CEP3) fig. 15 [0145-0147] located on the stem portion (CLP1) and protruding (diagonally) relative to (left/right) side surfaces of the stem portion (CLP1 of partition), wherein the formation of the partition (P) includes: forming a first layer (BNK) including a layer (BNK3) fig. 15 [0132] formed of a conductive first material (BNK3 comprising titanium) [0132]; forming a second layer (CPL1) fig. 15 [0129, 0139] including a layer (CPL1) formed of an insulating second material (CLP1 may be formed of silicon oxide) [0129, 0139] on the first layer (BNK); forming a third layer (comprising CEP3, CLP2, CLP3 and intervening layers) fig. 15 [0145-0147] including a layer (CEP3) (metal) [0146] formed of a third material (metal) [0146] on the second layer (CPL1); forming the top portion (comprising CEP3) by patterning the third layer (comprising CEP3) by a first etching process (process of etching CEP3) [see fig. 14, 0201]; forming the stem portion (CLP1) by patterning the second layer (CLP1) by a second etching process (process of etching CLP1) [see fig. 12, 0185]; and forming the bottom portion (BNK) by patterning the first layer (BNK3) by a third etching process (process of etching BNK) [see fig. 7, fig. 12, 0172, 0185], and an etching rate of the third material (CEP3) (metal) in the second etching process (process of etching CLP1) [see fig. 12, 0185] is lower (zero) than an (non-zero) etching rate of the second material (CLP1) in the second etching process (process of etching CLP1) [see fig. 12, 0185] (CEP3 is not etched in the second etching process [see fig. 12, 0185], and therefore, has a lower (zero) etching rate which is lower compared to the non-zero etching rate of CLP1). [AltContent: ][AltContent: textbox (CLP2)][AltContent: ][AltContent: textbox (CLP1)][AltContent: arrow][AltContent: textbox (Rib)][AltContent: textbox (Partition (P))][AltContent: arrow][AltContent: rect] PNG media_image1.png 355 632 media_image1.png Greyscale Annotated fig. 15 of Jung Regarding claim 2, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 1. Jung also teaches wherein the first layer (BNK3) fig. 15 [0173] includes a first bottom layer (BNK3) fig. 15 [0173] formed of the first material (metal = titanium [0173]) and a second bottom layer (BNK1) fig. 15 [0173] formed of a conductive material (Aluminum [0173]) different from the first material (titanium) [0173] and overlapping with the first bottom layer (BNK3). Regarding claim 3, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 2. Jung also teaches wherein the second bottom layer (BNK1) fig. 15 [0173] is thicker (overall) [0209] than the first bottom layer (BNK3) fig. 15 [0173]. Regarding claim 4, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 1. Jung also teaches wherein the third layer (comprising CEP3, CLP2, CLP3 and intervening layers) includes a first top layer (CEP3) fig. 15 [0145-0147] formed of the third material (CEP3 = metal) [0146] and a second top layer (CLP3) fig. 15 [0143] formed of a material (insulator such as silicon oxide) [0129] different from the third material (metal) [0146] and overlapping with the first top layer (CEP3). Regarding claim 5, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 4. Jung also teaches wherein one of the first top layer (CEP3 = metal) [0146] has conductive property (metal [0146]) and the second top layer (CLP2) has insulation property (insulator such as silicon oxide) [0129]. Regarding claim 6, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 2. Jung also teaches wherein the third layer (comprising CEP3, CLP2 and intervening layers) fig. 15 [0145-0147] includes a first top layer (CEP3) formed of the first material (CEP3 = metal) [0146, 0132] and a second top layer (CLP2) fig. 15 [0143] formed of a material (insulator such as silicon oxide) [0129] different from the first material (metal) and overlapping with the first top layer (CEP3). Regarding claim 7, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 1. Jung also teaches further comprising: forming an organic layer (EL2) fig. 15 [0125] covering the lower electrode (AE2) fig. 15 [0167] and emitting light [0125] in response to application of a voltage [0072]; and forming an upper electrode (CE2) fig. 15 [0127] covering the organic layer (EL2) and (directly) contacting the bottom portion (BNK) fig. 15 [0173]. Regarding claim 8, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 7. Jung also teaches further comprising: forming a sealing layer (TL2) fig. 15 [0144] continuously covering (at least portions of) a thin film (comprising EL2, CE2), which includes the organic layer (EL2) fig. 15 [0125] and the upper electrode (CE2) fig. 15 [0127], and the partition (P) (see annotated fig. 15 above). Regarding claim 9, Jung teaches a display device manufacturing method [see figs. 6-15, 0116], comprising: forming a lower electrode (AE2) fig. 6 [0167]; forming a rib (IL1) fig. 12 [0169] covering at least a part (right sidewall) of the lower electrode (AE2); and forming a partition (P) (see annotated fig. 15 below) on the rib (IL1), the partition (P) including a conductive bottom portion (BNK) fig. 15 [0173], an insulating stem portion (comprising CLP1) fig. 15 [0129, 0139] located on the bottom portion (BNK), and a top portion (comprising CEP3, CLP3) fig. 15 [0145-0147] located on the stem portion (CLP1) and protruding (diagonally) relative to (left/right) side surfaces of the stem portion (CLP1 of partition), wherein the formation of the partition (P) includes: forming a first layer (BNK 1, BNK3) including a layer (BNK1) fig. 15 [0132] formed of a conductive first material (BNK1 comprising aluminum) [0132]; forming a second layer (CPL1) fig. 15 [0129, 0139] including a layer (CPL1) formed of an insulating second material (CLP1 may be formed of silicon oxide) [0129, 0139] on the first layer (BNK 1, BNK3); forming a third layer (comprising BNK2, CEP3, CLP2, CLP3) fig. 15 [0129, 0145-0147] including a layer (BNK2) (metal) [0132] formed of a third material (titanium) [0146] on the second layer (CPL1); forming the top portion (comprising CEP3) by patterning the third layer (comprising CEP3) by a first etching process (process of etching CEP3) [see fig. 7, fig. 12, fig. 14, 0185, 0201]; forming the stem portion (CLP1) by patterning the second layer (CLP1) by a second etching process (process of etching CLP1) [see fig. 12, 0185]; and forming the bottom portion (BNK 1, BNK3) by patterning the first layer (BNK1) by a third etching process (defined as collective etching process of BNK 1-3 material) [see fig. 7, fig. 12, 0172, 0185], and an etching rate of the third material (BNK2) (titanium) [0132, 0172] in the third etching process (defined as collective process of etching BNK 1-3 material) [see fig. 7, fig. 12, 0172, 0185] is lower [0132, 0172] than an etching rate of the first material (BNK1 comprising aluminum) [0132] in the third etching process [see fig. 7, 0172] (BNK1 etched faster than BNK2 [0172] in step of etching process shown in fig. 7). [AltContent: arrow][AltContent: textbox (T2)][AltContent: arrow][AltContent: textbox (T1)][AltContent: connector][AltContent: connector][AltContent: ][AltContent: textbox (CLP2)][AltContent: ][AltContent: textbox (CLP1)][AltContent: arrow][AltContent: textbox (Rib)][AltContent: textbox (Partition (P))][AltContent: arrow][AltContent: rect] PNG media_image1.png 355 632 media_image1.png Greyscale Annotated fig. 15 of Jung Regarding claim 10, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 9. Jung also teaches wherein the first layer (BNK 1, BNK3) fig. 15 [0132] includes a first bottom layer (BNK1) [0132] formed of the first material (aluminum) [0132] and a second bottom layer (BNK3) fig. 15 [0132] formed of a conductive material (titanium) [0132] different from the first material (aluminum) [0132] and overlapping with the first bottom layer (BNK1). Regarding claim 11, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 10. Jung also teaches wherein the (middle of) second bottom layer (BNK3) fig. 15 [0173] is thicker (in middle, has thickness T2) than the (corner of) first bottom layer (BNK1) fig. 15 [0173] (at corner, has infinitesimal thickness T1) (T1 < T2; as defined in annotated fig. 15 above). Regarding claim 12, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 9. Jung also teaches the third layer (comprising BNK2, CEP3, CLP2, CLP3) fig. 15 [0129, 0145-0147] includes a first top layer (BNK2) [0132] formed of the third material (titanium) [0132] and a second top layer (CLP2) fig. 15 [0143, 0129] formed of a material (silicon oxide) [0129] different from the third material (titanium) [0132] and overlapping with (right portions of) the first top layer (BNK2). Regarding claim 13, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 12. Jung also teaches wherein one of the first top layer (BNK2) [0132] has conductive property (titanium metal is conductive) [0132] and the and the second top layer (silicon oxide) [0129, 0143] has insulation property (silicon oxide is insulative) [0129]. Regarding claim 14, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 10. Jung also teaches wherein the third layer (comprising BNK2, CEP3, CLP2) fig. 15 [0129, 0145-0147] includes a first top layer (CEP3) [0146] formed of the first material (metal) [0146] and a second top layer (CLP3) fig. 15 [0129, 0143] formed of a material (silicon oxide) [0129] different from the first material (metal) and overlapping with the first top layer (CEP3). Regarding claim 15, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 9. Jung also teaches further comprising: forming an organic layer (EL2) fig. 15 [0125] covering the lower electrode (AE2) fig. 15 [0167] and emitting light [0125] in response to application of a voltage [0072]; and forming an upper electrode (CE2) fig. 15 [0127] covering the organic layer (EL2) and (directly) contacting the bottom portion (BNK 1) fig. 15 [0173]. Regarding claim 16, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 15. Jung also teaches further comprising: forming a sealing layer (TL2) fig. 15 [0144] continuously covering (at least portions of) a thin film (comprising EL2, CE2), which includes the organic layer (EL2) fig. 15 [0125] and the upper electrode (CE2) fig. 15 [0127], and the partition (P) (see annotated fig. 15 above). Regarding claim 17, Jung teaches a display device manufacturing method [see figs. 6-15, 0116], comprising: forming a lower electrode (AE2) fig. 6 [0167]; forming a rib (IL1) fig. 12 [0169] covering at least a part (right sidewall) of the lower electrode (AE2); and forming a partition (P) (see annotated fig. 15 below) on the rib (IL1), the partition (P) including a conductive bottom portion (BNK) fig. 15 [0173], an insulating stem portion (comprising CLP1) fig. 15 [0129, 0139] located on the bottom portion (BNK), and a top portion (comprising CEP3, CLP3) fig. 15 [0145-0147] located on the stem portion (CLP1) and protruding (diagonally) relative to (left/right) side surfaces of the stem portion (CLP1 of partition), wherein the formation of the partition (P) includes: forming a first layer (BNK1, BNK3) including a layer (BNK3) fig. 15 [0132] formed of a conductive first material (BNK3 comprising titanium) [0132]; forming a second layer (CPL1) fig. 15 [0129, 0139] including a layer (CPL1) formed of an insulating second material (CLP1 may be formed of silicon oxide) [0129, 0139] on the first layer (BNK 1, BNK3); forming a third layer (comprising BNK2, CEP3, CLP2, CLP3) fig. 15 [0129, 0145-0147] including a layer (BNK2) (metal) [0132] formed of the first material (titanium) [0146] on the second layer (CPL1); forming the top portion (comprising CEP3) by patterning the third layer (comprising CEP3) by a first etching process (process of etching CEP3) [see fig. 7, fig. 12, fig. 14, 0185, 0201]; forming the stem portion (CLP1) by patterning the second layer (CLP1) by a second etching process (process of etching CLP1) [see fig. 12, 0185]; and forming the bottom portion (BNK 1, BNK3) by patterning the first layer (BNK3) by a third etching process (defined as collective etching process of BNK 1-3 material) [see fig. 7, fig. 12, 0172, 0185], forming a third layer (comprising CEP3, CLP2, CLP3 and intervening layers) fig. 15 [0145-0147] including a layer (CEP3) (metal) [0146] formed of a third material (metal) [0146] on the second layer (CPL1); forming the top portion (comprising CEP3) by patterning the third layer (comprising CEP3) by a first etching process (process of etching CEP3) [see fig. 14, 0201]; forming the stem portion (CLP1) by patterning the second layer (CLP1) by a second etching process (process of etching CLP1) [see fig. 12, 0185]; and forming the bottom portion (BNK) by patterning the first layer (BNK1) by a third etching process (process of etching BNK) [see fig. 12, 0185], and and the layer (comprising BNK2) formed of the first material (titanium) included in the third layer (comprising BNK2, CEP3, CLP2, CLP3) is formed to be thicker (in middle, has thickness T1) than the layer (BNK3) formed of the first material (titanium) included in the first layer (BNK3 with BNK1) (at corner, has infinitesimal thickness T2) (T2< T1; as defined in annotated fig. 15 below). [AltContent: arrow][AltContent: connector][AltContent: connector][AltContent: arrow][AltContent: ][AltContent: textbox (CLP2)][AltContent: ][AltContent: textbox (CLP1)][AltContent: arrow][AltContent: textbox (Rib)][AltContent: textbox (Partition (P))][AltContent: arrow][AltContent: rect][AltContent: textbox (T1)][AltContent: textbox (T2)][AltContent: ][AltContent: textbox (CLP2)][AltContent: ][AltContent: textbox (CLP1)][AltContent: arrow][AltContent: textbox (Rib)][AltContent: textbox (Partition (P))][AltContent: arrow][AltContent: rect] PNG media_image1.png 355 632 media_image1.png Greyscale Annotated fig. 15 of Jung Regarding claim 18, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 17. Jung also teaches wherein the first layer (BNK 1, BNK3) fig. 15 [0132] includes a first bottom layer (BNK3) [0132] formed of the first material (titanium) [0132] and a second bottom layer (BNK1) fig. 15 [0132] formed of a conductive material (aluminum) [0132] different from the first material (titanium and aluminum different metals [0132]) and overlapping with the first bottom layer (BNK3). Regarding claim 19, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 18. Jung also teaches wherein the second bottom layer (BNK1) fig. 15 [0173] is thicker (overall) [0209] than the first bottom layer (BNK3) fig. 15 [0173]. Regarding claim 20, Jung teaches the display device manufacturing method [see figs. 6-15, 0116] of claim 17. Jung also teaches further comprising: forming an organic layer (EL2) fig. 15 [0125] covering the lower electrode (AE2) fig. 15 [0167] and emitting light [0125] in response to application of a voltage [0072]; and forming an upper electrode (CE2) fig. 15 [0127] covering the organic layer (EL2) and (directly) contacting the bottom portion (BNK 1) fig. 15 [0173]. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ishida (US-20240130167-A1), Fukuda (US-20230240118-A1), Imai (US-20230413645-A1), Fukuda (US-20230354674-A1), Choung (US-20220077251-A1), Huang (US-20220344421-A1), Nitta (US-20220199937-A1), and Yoo (US-20240121992-A1) all feature other examples of display devices with etched, multilayered partitions. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEAN AYERS WINTERS/Examiner, Art Unit 2892 02/09/2026 /NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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Prosecution Timeline

Dec 11, 2023
Application Filed
Feb 09, 2026
Non-Final Rejection — §102 (current)

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+24.7%)
3y 5m
Median Time to Grant
Low
PTA Risk
Based on 112 resolved cases by this examiner. Grant probability derived from career allow rate.

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