DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 9-10 and 14-16 are objected to because of the following informalities:
Claims 9 and 10 each recite similar language: “wherein the first [or second] row decoder region [or page buffer region] where a first row decoder for controlling the memory cells included in the memory chip structure is disposed overlaps a region…”. The subject “first row decoder region” and verb “overlaps” has been split up by a lengthy description of the region, which makes it unclear and confusing. Examiner suggests rearranging the limitation to clarify the meaning, such as: “wherein the first row decoder region includes a first row decoder for controlling the memory cells included in the memory chip structure, and wherein the first row decoder region overlaps a region between…” Claims 14-15 have similar language that needs similar correction.
Claim 16 has a typo “regains,” which Examiner believes should be “regions” in line 13.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Na et al. (U.S. Publication No. 2022/0310541).
Regarding claim 1, Na teaches a semiconductor memory device comprising:
a first stack structure (Fig. 2A, first stack 100);
a plurality of first slits (Fig. 1, slits SS1; Fig. 2A, slits 148) passing through the first stack structure in a vertical direction and extending in a first horizontal direction orthogonal to the vertical direction (see Fig. 1-2);
a first source line layer (source line 115) formed over a top portion of the first stack structure (Fig. 2A);
a second source line layer (215) formed over the first source line layer (Fig. 2A);
a second stack structure (Fig. 2A-B, second stack 200) overlapping with the first stack structure in the vertical direction (Fig. 2A-B); and
a plurality of second slits (Fig. 1, slits SS2; Fig. 2B, slits 248) passing through the second stack structure in the vertical direction and extending in a second horizontal direction orthogonal to the vertical direction (Fig. 1 and 2B).
Regarding claim 2, Na teaches the semiconductor memory device of claim 1, wherein the first horizontal direction and the second horizontal direction are orthogonal to each other (Fig. 1).
Regarding claim 3, Na teaches the semiconductor memory device of claim 1, further comprising:
a plurality of first cell plugs (Fig. 2B, cell plugs 136) extending in the vertical direction within the first stack structure and contacting the first source line layer (Fig. 2B); and
a plurality of second cell plugs (Fig. 2A, cell plugs 236) extending in the vertical direction within the second stack structure and contacting the second source line layer (Fig. 2A).
Regarding claim 4, Na teaches the semiconductor memory device of claim 1, wherein each of the first stack structure and the second stack structure includes interlayer insulating layers and word line patterns alternately stacked in the vertical direction (see Fig. 3A, layers 130 and 127M; Fig. 3B, layers 230 and 227M).
Regarding claim 5, Na teaches the semiconductor memory device of claim 1, further comprising:
a memory chip structure including a peripheral circuit under the first stack structure (Fig. 2A< peripheral circuit 10).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Na in view of Takekida (U.S. Publication No. 2022/0246213)
Regarding claim 6, Na teaches the semiconductor memory device of claim 1, further comprising:
a lower memory chip structure (Fig. 2A, lower structure 100/10) including a first peripheral circuit (peripheral circuit in 10) for operating memory cells included in the first stack structure under the first stack structure (Fig. 2A); and
an upper memory chip structure (200).
Na does not teach the upper memory chip structure including a second peripheral circuit for operating memory cells included in the second stack structure on the second stack structure. However, Takekida teaches a similar memory device in which the upper structure has a second peripheral circuit for operating the memory cells (Takekida Fig. 7, upper structure 300/400 includes peripheral circuit in 400). It would have been obvious to a person of skill in the art at the time of the effective filing date that a second peripheral circuit could have been included in the upper chip because this allows for shorter/lower resistance connections between each controller and their respective memory chip, and allows for parallel control of each memory stack instead of shared control by a single controller.
Claims 7, 9, 12, 14-16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Na in view of Fastow et al. (U.S. Publication No. 2019/0043836).
Regarding claim 7, Na teaches a semiconductor memory device comprising:
a first memory chip structure (Fig. 1, chip 100) including first and second plane regions (101A add 101B);
a second memory chip structure (Fig. 1, chip 200) bonded to a top surface of surface of the first memory chip structure in a vertical direction (Fig. 1) and including third and fourth plane regions (201A and 201B); and
a third memory chip structure (Fig. 1, chip 10) bonded to a bottom surface of the first memory chip structure in the vertical direction (Fig. 1), and including first and second page buffer regions (page buffers 6a, 6b) where a page buffer for controlling an operation of memory cells included in the first memory chip structure and the second memory chip structure is disposed (paragraph [0028]), and first and second row decoder regions (row decodes 2a, 2b) where a row decoder for controlling the operation of the memory cells is disposed (paragraph [0028]),
wherein the first memory chip structure includes first slits (slits SS1) passing through the plurality of first stack structures in the vertical direction and extending in a first horizontal direction orthogonal to the vertical direction (Fig. 1 and 2A), and
wherein the second memory chip structure includes second slits (Fig. 1, slits SS2) passing through the plurality of second stack structures in the vertical direction and extending in a second horizontal direction orthogonal to the vertical direction and the first horizontal direction (Fig. 1 and 2B).
Na does not specifically teach that the first and second planes each including a plurality of first stack structures; or the third and fourth planes each including a plurality of second stack structures. However, Fastow teaches that each plane of a memory chip has a plurality of cells/stacks (Fastow paragraph [0034]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the planes of Na would have had several cells/stacks within the because Fastow teaches that grouping several cells into a plane has various read/write performance improvements (see Fastow paragraph [0034]).
Regarding claim 9, Na in view of Fastow teaches the semiconductor memory device of claim 7, wherein the first row decoder region (region around decoder 2a) where a first row decoder for controlling the memory cells included in the memory chip structure is disposed (Fig. 1-2A) overlaps a region between the plurality of first stack structures of the first plane region and a region between the plurality of first stack structures of the second plane region (see Fig. 1), and
wherein the second row decoder region (region around decoder 2b) where a second row decoder for controlling the memory cells included in the second memory chip structure is disposed overlaps a region between the plurality of second stack structures of the third plane region and a region between the plurality of second stack structures of the fourth plane region (se Fig. 1).
Regarding claim 12, Na teaches a semiconductor memory device comprising:
a first memory chip structure (Fig. 8, chip 100) including first to fourth stack structures (101A, 101B, see paragraph [0025], although only 2 stacks are shown, 4 is contemplated within the embodiments) arranged in a matrix form;
a second memory chip structure (chip 200) bonded to a top surface of the first memory chip structure in a vertical direction (Fig. 8) and including fifth to eighth stack structures arranged in the matrix form (stacks 201A, 201B, see paragraph [0025]); and
a third memory chip structure (chip 10) bonded to a bottom surface of the first memory chip structure in the vertical direction (Fig. 8), and including first and second page buffer regions (6a1, 6b1) where a page buffer for controlling an operation of memory cells included in the first memory chip structure and the second memory chip structure is disposed (Fig. 8), and first to eighth row decoder regions (only 4 are shown, 2a1 and 2b1, because only 4 memory cells are shown 101a/b and 201a/b; however, 8 or more memory cells are contemplated, see paragraph [0025]) where a row decoder for controlling the operation of the memory cells is disposed (Fig. 8),
wherein the first memory chip structure includes first slits (SS1) passing through the plurality of first stack structures in the vertical direction and extending in a first horizontal direction orthogonal to the vertical direction (Fig. 8), and
wherein the second memory chip structure includes second slits (SS2) passing through the plurality of second stack structures in the vertical direction and extending in a second horizontal direction orthogonal to the vertical direction and the first horizontal direction (Fig. 8).
Na teaches that there can be additional stacks, but does not clearly state that there are at least 4 stacks arranged in a matrix on a chip. However, Fastow teaches that each memory chip in a stack has at least four stacks (Fastow Fig. 4B). It would have been obvious to a person of skill in the art at the time of the effective filing date that the planes of Na would have had several cells/stacks within the because Fastow teaches that grouping several cells into a plane has various read/write performance improvements (see Fastow paragraph [0034]).
Regarding claim 14, Na in view of Fastow teaches the semiconductor memory device of claim 12, wherein the first row decoder region and the second row decoder region where the row decoder respectively corresponding to the first stack structure and the second stack structure is disposed overlap with a region between the first stack structure and the second stack structure (see Fig. 8, decoders 2a-2a overlap with regions 101A and 101B),
wherein the third row decoder region and the fourth row decoder region where the row decoder respectively corresponding to the third stack structure and the fourth stack structure overlap with a region between the third stack structure and the fourth stack structure (Fig. 8, row decoders overlap with respective stacks regardless of how many stacks are present),
wherein the fifth row decoder region and the sixth row decoder region where the row decoder respectively corresponding to the fifth stack structure and the sixth stack structure overlap with a region between the fifth stack structure and the sixth stack structure (see Fig. 8, decoders 2a-2a overlap with regions 201A and 201B), and
wherein the seventh row decoder region and the eighth row decoder region where the row decoder respectively corresponding to the seventh stack structure and the eighth stack structure overlap with a region between the seventh stack structure and the eighth stack structure (Fig. 8, row decoders overlap with respective stacks regardless of how many stacks are present).
Regarding claim 15, Na in view of Fastow teaches the semiconductor memory device of claim 14, wherein the first page buffer region where a first page buffer for controlling the memory cells included in the first memory chip structure is disposed, is disposed between the fifth row decoder region and the sixth row decoder region or between the seventh row decoder region and the eighth row decoder region, and
wherein the second page buffer region where a second page buffer for controlling the memory cells included in the second memory chip structure is disposed, is disposed between the first row decoder region and the second row decoder region or between the third row decoder region and the fourth row decoder region.
Na does not show the page buffer arrangement for a 2-dimensional array, only a 1-dimensional array, and therefore does not show the claimed page buffer spacing. However, Fastow teaches a 2-dimensional array wherein the first page buffer region where a first page buffer for controlling the memory cells included in the first memory chip structure is disposed, is disposed between the fifth row decoder region and the sixth row decoder region or between the seventh row decoder region and the eighth row decoder region (see Fastow Fig. 4A-4B, page buffers SPB are between each adjacent set of stacks 0, 1, 2, 3), and
wherein the second page buffer region where a second page buffer for controlling the memory cells included in the second memory chip structure is disposed, is disposed between the first row decoder region and the second row decoder region or between the third row decoder region and the fourth row decoder region (see Fastow Fig. 4A-4B, page buffers SPB are between each adjacent set of stacks 0, 1, 2, 3). It would have been obvious to a person of skill in the art at the time of the effective filing date that the page buffers of Na could have been between adjacent stacks in a 2-dimensional array because they are positioned at the edges of the stacks, and when additional stacks are placed adjacent those edges, they would inherently be between the sets of stacks.
Regarding claim 16, Na teaches a semiconductor memory device comprising:
a first memory chip structure (Fig. 1, chip 100) including first and second plane regions (101A, 101B);
a second memory chip structure (chip 200) bonded to a top surface of surface of the first memory chip structure in a vertical direction and including third and fourth plane regions (201A, 201B); and
a third memory chip structure (10) bonded to a bottom surface of the first memory chip structure in the vertical direction (Fig. 8), and including first to fourth page buffer regions (6a1, 6b1, see paragraph [0025], can be more stacks and therefore more page buffers) where a page buffer for controlling an operation of memory cells included in the first memory chip structure and the second memory chip structure is disposed (Fig. 8), and first to fourth row decoder regains (2a1, 2a2) where a row decoder for controlling the operation of the memory cells is disposed (see Fig. 8 and paragraph [0025]),
wherein the first memory chip structure includes first slits (SS1) passing through the plurality of first stack structures in the vertical direction and extending in a first horizontal direction orthogonal to the vertical direction (Fig. 8), and
wherein the second memory chip structure includes second slits (SS2) passing through the plurality of second stack structures in the vertical direction and extending in a second horizontal direction orthogonal to the vertical direction and the first horizontal direction (Fig. 8).
Na does not teach the first and second planes each including a plurality of first stack structures, or the third and fourth planes each including a plurality of second stack structures. However, Fastow teaches that each plane of a memory chip has a plurality of cells/stacks (Fastow paragraph [0034]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the planes of Na would have had several cells/stacks within the because Fastow teaches that grouping several cells into a plane has various read/write performance improvements (see Fastow paragraph [0034]).
Regarding claim 18, Na in view of Fastow teaches the semiconductor memory device of claim 16, wherein the first to fourth row decoder regions overlap with an external region adjacent to the first and second plane regions or the third and fourth plane regions (see Fig. 8, row decoders 2a_2b, 2a_1b, 2b_1a and 2a_2a).
Regarding claim 19, Na in view of Fastow teaches the semiconductor memory device of claim 16, wherein the first page buffer region where a first page buffer for controlling the memory cells included in the first plane region is disposed, is disposed to overlap with a region where the first plane region and the third plane region overlap (Fig. 8, page buffer region 6a1),
wherein the second page buffer region where a second page buffer for controlling the memory cells included in the second plane region is disposed, is disposed to overlap with a region where the second plane region and the fourth plane region overlap (Fig. 8, page buffer region 6b1),
wherein the third page buffer region where a third page buffer for controlling the memory cells included in the third plane region is disposed, is disposed to overlap with a region where the second plane region and the third plane region overlap (Fig. 8, when more stacks are present, page buffers would also be under those overlapping stacks, see Fastow Fig. 4B), and
wherein the fourth page buffer region where a fourth page buffer for controlling the memory cells included in the fourth plane region is disposed, is disposed to overlap with a region where the first plane region and the fourth plane region overlap (Fig. 8, when more stacks are present, page buffers would also be under those overlapping stacks, see Fastow Fig. 4B).
Claims 8, 13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Na in view of Fastow, further in view of Sung et al. (KR 2022-0034273).
Regarding claim 8, Na in view of Fastow teaches the semiconductor memory device of claim 7, wherein a plurality of first source line layers corresponding to the plurality of respective first stack structures (see Na Fig. 1 and 2A, each stack structure has a source line 115),
wherein a plurality of second source line layers corresponding to the plurality of respective second stack structures (see Na Fig. 1 and 2A, each stack structure has a source line 215).
Na does not teach that the source lines are exposed on a top surface of surface of the first memory chip structure and bottom surface of the second memory chip structure, or wherein the plurality of first source line layers and the plurality of second source line layers directly contact each other. Sung teaches that the source lines of the lower chip and upper chip are exposed and directly contact each other (Suing Fig. 5, CSL of upper and lower chips CAR1 and CAR2 are in direct contact). It would have been obvious to a person of skill in the art at the time of the effective filing date that the source lines could have been exposed and in direct contact because this allows a much lower resistance connection that the via/pad bonded connection of Na (see Na Fig. 2A).
Regarding claim 13, Na in view of Fastow teaches the semiconductor memory device of claim 12, wherein a plurality of first source line layers corresponding to each of the first to fourth stack structures are on a top surface of the first memory chip structure (see Fig. 8 and 2A, each stack structure has a source line 115);
wherein a plurality of second source line layers corresponding to each of the fifth to eighth stack structures are on a bottom surface of the second memory chip structure (see Fig. 8 and 2A, each stack structure has a source line 215).
Na does not teach that the source lines are exposed on a top surface of surface of the first memory chip structure and bottom surface of the second memory chip structure, or wherein the plurality of first source line layers and the plurality of second source line layers directly contact each other. Sung teaches that the source lines of the lower chip and upper chip are exposed and directly contact each other (Suing Fig. 5, CSL of upper and lower chips CAR1 and CAR2 are in direct contact). It would have been obvious to a person of skill in the art at the time of the effective filing date that the source lines could have been exposed and in direct contact because this allows a much lower resistance connection that the via/pad bonded connection of Na (see Na Fig. 2A).
Regarding claim 17, Na in view of Fastow teaches the semiconductor memory device of claim 16, wherein a plurality of first source line layers corresponding to each of the first to fourth stack structures are on a top surface of the first memory chip structure (see Fig. 8 and 2A, each stack structure has a source line 115);
wherein a plurality of second source line layers corresponding to each of the fifth to eighth stack structures are on a bottom surface of the second memory chip structure (see Fig. 8 and 2A, each stack structure has a source line 215).
Na does not teach that the source lines are exposed on a top surface of surface of the first memory chip structure and bottom surface of the second memory chip structure, or wherein the plurality of first source line layers and the plurality of second source line layers directly contact each other. Sung teaches that the source lines of the lower chip and upper chip are exposed and directly contact each other (Suing Fig. 5, CSL of upper and lower chips CAR1 and CAR2 are in direct contact). It would have been obvious to a person of skill in the art at the time of the effective filing date that the source lines could have been exposed and in direct contact because this allows a much lower resistance connection that the via/pad bonded connection of Na (see Na Fig. 2A).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Na in view of Sung.
Regarding claim 20, Na teaches a method of manufacturing a semiconductor memory device, the method comprising:
forming a first stack structure (Fig. 2A and 8, first stack 100), and forming, by the first stack structure, a lower stack structure including first interlayer insulating layers and second word line patterns alternately stacked in a vertical direction (see Fig. 3A, 130 and 127M), first cell plugs having an end extending upwardly by passing through the lower stack structures (Fig. 2A, cell plugs 136), a plurality of first slits extending in a first horizontal direction orthogonal to the vertical direction by passing through the lower stack structure in the vertical direction (Fig. 2B and 8, slits SS1), and a first source line layer (source line 115) stacked on the lower stack structure and connected to the end of first cell plugs (Fig. 2B); and
forming a second stack structure (200) on the first stack structure, and forming a second source line layer (215) contacting the first source line layer, an upper stack structure including second interlayer insulating layers and third word line patterns alternately stacked in the vertical direction (Fig. 3B, 230 and 227M), second cell plugs (Fig. 2A, plugs 236) extending downwardly by passing through the upper stack structure and having an end contacting the second source line layer (Fig. 2A), a plurality of second slits extending in a second horizontal direction orthogonal to the vertical direction and the first horizontal direction by passing through the upper stack structure in the vertical direction (Fig. 2B and 8, SS2).
Na does not teach the second source line is directly contacting the first source line layer. Sung teaches that the source lines of the lower chip and upper chip are exposed and directly contact each other (Suing Fig. 5, CSL of upper and lower chips CAR1 and CAR2 are in direct contact). It would have been obvious to a person of skill in the art at the time of the effective filing date that the source lines could have been exposed and in direct contact because this allows a much lower resistance connection that the via/pad bonded connection of Na (see Na Fig. 2A).
Allowable Subject Matter
Claims 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 10-11, the prior art, alone or in combination, fails to teach or suggest wherein the first page buffer region overlaps at least one first stack structure among the plurality of first stack structures, and wherein the second page buffer region overlaps a region between the plurality of first stack structures of the first plane region and a region between the plurality of first stack structures of the second plane region.
Conclusion
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/EVAN G CLINTON/ Primary Examiner, Art Unit 2899