DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested: “SEMICONDUCTOR DEVICE HAVING A SOURCE/DRAIN PATTERN INCLUDING MULTIPLE LAYERS WITH DIFFERENT CONDUCTIVITY TYPE.”
If Applicant does not agree with the suggested title above, Applicant must provide a new title that clearly reflects the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5-8, 11, 12, 14, 15 and 18 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Park et al. (US Pub. 2022/0285511; hereinafter “Park”).
Regarding Claim 1, Park discloses a semiconductor device comprising: an active pattern (active region 105 and a plurality of channel layers 140) which includes a first lower pattern 105 (page 2, paragraph 24) and a plurality of first sheet patterns 140 (page 2, paragraph 29), wherein the first lower pattern 105 extends in a first direction (X-direction; page 2, paragraph 27), and the plurality of first sheet patterns 140 are spaced apart from the first lower pattern 105 in a second direction (Z-direction; page 2, paragraph 29) crossing the first direction (X-direction) (see fig. 6B); a gate structure 160, which includes a gate electrode 165 and a gate spacer 164 (page 4, paragraph 44) extending in a third direction (Y-direction; page 4, paragraph 43) intersecting the first direction (X-direction) and the second direction (Z-direction) (see figs. 1 and 6B), disposed on the active pattern (see fig. 25A); a first source/drain pattern 150Bd (left one) (page 3, paragraph 65) disposed adjacent to a first side (left side) of the gate structure 160 (see fig. 6B); and a second source/drain pattern 150Bd (right one) which is spaced apart from the first source/drain pattern 150Bd (left one) with the gate structure 160 interposed therebetween (see fig. 6B), wherein the first source/drain pattern 150Bd (left one) includes: a lower layer 152B including a first conductivity type (n-type; page 4, paragraphs 39 and 40) and disposed on the first lower pattern 105 (see fig. 6B), and an upper layer 154B2 including a second conductivity type (p-type; page 4, paragraphs 39 and 40), which is different from the first conductivity type (pages 4, paragraphs 39 and 40), and disposed on the lower layer 152B (see fig. 6B), wherein the second source/drain pattern 150Bd (right one) has the second conductivity type (upper layers 154B1 and 154B2 have p-type conductivity; page 4, paragraph 40).
Regarding Claim 3, Park discloses further comprising: a first source/drain contact 180 (page 5, paragraph 49) disposed on the first source/drain pattern 150Bd (left one), wherein a first lower surface (bottom surface) of the first source/drain contact 180 is disposed inside the upper layer 154B2 (page 5, paragraph 50; see fig. 6B).
Regarding Claim 5, Park discloses wherein the plurality of first sheet patterns 140 do not include impurities of the first conductivity type and impurities of the second conductivity type (the plurality of channel layers 140 may be formed of a semiconductor material such as Si, SiGe, or Ge, and in some embodiments, the plurality of channel layers 140 may include impurity regions; page 2, paragraph 30; because impurity regions are described as present only in some embodiments, it follows that other embodiments exist in which the plurality of channel layers 140 do not include impurity regions).
Regarding Claim 6, Park discloses wherein the second source/drain pattern 150Bd (right one) includes a plurality of films (154B1, 154B2) of the second conductivity type (p-type; page 4, paragraph 40).
Regarding Claim 7, Park discloses further comprising: an internal spacer 130 (page 5, paragraph 48) disposed between the first source/drain pattern 150Bd (left one) and the gate electrode 165, and between the plurality of first sheet patterns 140 (see fig. 6B).
Regarding Claim 8, Park discloses wherein a first width (vertical thickness in Z-direction), in the second direction (Z-direction), of a first portion of the gate electrode 165 disposed above the plurality of first sheet patterns 140 on the basis of an upper surface of the first lower pattern 105 is greater than a second width (vertical thickness in Z-direction), in the second direction (Z-direction), of a second portion of the gate electrode 165 disposed between the plurality of first sheet patterns 140 (see fig. 6B).
Regarding Claim 11, Park discloses wherein an upper surface of the first source/drain pattern 150Bd (left one) and an upper surface of the second source/drain pattern 150Bd (right one) are disposed above an uppermost surface of the plurality of first sheet patterns 140, on the basis of an upper face of the first lower pattern 105 (see fig. 6B).
Regarding Claim 12, Park discloses wherein the upper layer 154B2 of the first source/drain pattern 150Bd (left one) is not in contact with side surfaces of the plurality of first sheet patterns 140 (see fig. 6B), and the lower layer 152B of the first source/drain pattern 150Bd (right one) is in contact with the plurality of first sheet patterns 140 (see fig. 6B).
Regarding Claim 14, Park discloses a semiconductor device comprising: an active pattern (active region 105 and a plurality of channel layers 140) which includes a first lower pattern 105 (page 2, paragraph 24) and a plurality of first sheet patterns 140 (page 2, paragraph 29), wherein the first lower pattern 105 extends in a first direction (X-direction; page 2, paragraph 27), and the plurality of first sheet patterns 140 are spaced apart from the first lower pattern 105 in a second direction (Z-direction; page 2, paragraph 29); a gate structure 160, which includes a gate electrode 165 and a gate spacer 164 (page 4, paragraph 44) extending in a third direction (Y-direction; page 4, paragraph 43) intersecting the first direction (X-direction) and the second direction (Z-direction), disposed on the active pattern (see figs. 1 and 6B); a first source/drain pattern 150Bd (left one) (page 3, paragraph 65) disposed adjacent to a first side (left side) of the gate structure 160 (see fig. 6B); and a second source/drain pattern 150Bd (right one) which is spaced apart from the first source/drain pattern 150Bd (left one) with the gate structure 160 interposed therebetween (see fig. 6B), wherein the first source/drain pattern 150Bd (left one) includes: a first layer 152B including a first conductivity type (n-type; page 4, paragraphs 39 and 40); and a second layer 154B2 including a second conductivity type (p-type; page 4, paragraphs 39 and 40) different from the first conductivity type (page 4, paragraphs 39 and 40), wherein the second source/drain pattern 150Bd (right one) has the second conductivity type (upper layers 154B1 and 154B2 have p-type conductivity; page 4, paragraph 40), and wherein side surfaces of the plurality of first sheet patterns 140 are in contact with the first layer 152B and the second source/drain pattern 150Bd (right one), and are not in contact with the second layer 154B2 (see fig. 6B).
Regarding Claim 15, Park discloses wherein the second layer 154B2 of the first source/drain pattern 150Bd (left one) overlaps the plurality of first sheet patterns 140 in the first direction (X-direction) (see fig. 6B).
Regarding Claim 18, Park discloses wherein the plurality of first sheet patterns 140 do not include impurities of the first conductivity type and impurities of the second conductivity type (the plurality of channel layers 140 may be formed of a semiconductor material such as Si, SiGe, or Ge, and in some embodiments, the plurality of channel layers 140 may include impurity regions; page 2, paragraph 30; because impurity regions are described as present only in some embodiments, it follows that other embodiments exist in which the plurality of channel layers 140 do not include impurity regions).
Allowable Subject Matter
Claims 2, 4, 9, 10, 13, 16, 17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 recites the first source/drain pattern further comprises a capping film including the first conductivity type and disposed on the upper layer.
Claim 4 recites a height of the first lower surface of the first source/drain contact and a height of a second lower surface of the second source/drain contact are different from each other, on the basis of an upper surface of the first lower pattern.
Claim 9 recites a width of the first source/drain pattern is greater than a width of the second source/drain pattern.
Claim 10 recites a lower surface of the first source/drain pattern is disposed lower than a lower surface of the second source/drain pattern, on the basis of an upper surface of the first lower pattern.
Claim 13 recites the lower layer at least partially surrounds a side surface and a lower surface of the upper layer.
Claim 16 recites the first source/drain pattern further includes a third layer including the first conductivity type, and the second layer is surrounded by the first layer and the third layer.
Claim 19 recites the second source/drain pattern includes a single film of the second conductivity type.
These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record.
Claim 17 depends from claim 16, so it is objected for the same reason.
Claim 20 is allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 20 recites a third layer including the first conductivity type and disposed on the second layer, wherein the first layer surrounds a side surface and a lower surface of the second layer, wherein the third layer covers an upper surface of the second layer, and wherein the first source/drain contact penetrates the third layer, and a lower surface of the first source/drain contact is disposed inside the second layer.
These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM.
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 January 29, 2026