Prosecution Insights
Last updated: October 25, 2026
Application No. 18/534,862

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

Final Rejection §103
Filed
Dec 11, 2023
Examiner
LINDSEY, COLE LEON
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Macronix International Co., Ltd.
OA Round
2 (Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
124 granted / 139 resolved
+21.2% vs TC avg
Moderate +12% lift
Without
With
+12.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
18 currently pending
Career history
170
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
53.3%
+13.3% vs TC avg
§102
29.6%
-10.4% vs TC avg
§112
15.4%
-24.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 139 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 08/31/2026 have been fully considered but they are not persuasive. Applicant’s arguments, see section titled “Rejection of Claims 1, 7, 8, and 10,” filed 08/31/2026, with respect to the rejection of claims 1-13 under 35 U.S.C. 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the combination of Chen et al. (US20100206538A1, hereinafter Chen) in view of Tangring (US20220320404A1). Regarding amended claim 1, Chen teaches a semiconductor structure comprising: a semiconductor substrate (Figs. 10/6 heat source 64 and par. 26 teaches that “the heat source 64 can be a central processing unit or a chip installed on the circuit board 63.” Examiner notes fig. 6 illustrates details omitted in the embodiment represented in fig. 10 and so reference will be made to both figures for clarity); and a heat dissipating component disposed on a surface of the semiconductor substrate (Fig. 10/6 thermal module 100 disposed on surface of heat source 64), the heat dissipating component comprising a plurality of protrusions, each of the protrusions comprising a plurality of first sections and a plurality of second sections (Fig. 10 thermal module 100 has protruding portions 104 with a curved edge and sawtooth-shaped protruding portion 102 with a slanted edge), wherein a dimension of the first sections is different from a dimension of the second sections (Fig. 10 would reasonably suggest and disclose to a person of ordinary skill in the art that the curved edge of protruding portions 104 has a different length than the slanted edge of the sawtooth-shaped protruding portion 102, see MPEP 2125.I). Chen does not appear to teach wherein a material of the protrusions of the heat dissipating component comprises graphite sheet, Si, phase change material, liquid metal paste, thermal paste, or AIN. Tangring teaches wherein a material of the protrusions of the heat dissipating component comprises graphite sheet, Si, phase change material, liquid metal paste, thermal paste, or AIN (Par. 25 teaches that “the heat dissipating structure is formed at least in places with…aluminum nitride”). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen with the teachings of Tangring because, as both Chen and Tangring present suitable materials for use in a heat dissipation structure, it would have been obvious to substitute Chen’s aluminum heat dissipation material with Tangring’s aluminum nitride heat dissipation material to achieve the predictable result of forming Chen’s thermal fins from aluminum nitride. See below for full claims mapping. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 7-8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Chen (US20100206538A1) in view of Tangring (US20220320404A1). Regarding claim 1, Chen teaches a semiconductor structure comprising: a semiconductor substrate (Figs. 10/6 heat source 64 and par. 26 teaches that “the heat source 64 can be a central processing unit or a chip installed on the circuit board 63.” Examiner notes fig. 6 illustrates details omitted in the embodiment represented in fig. 10 and so reference will be made to both figures for clarity); and a heat dissipating component disposed on a surface of the semiconductor substrate (Fig. 10/6 thermal module 100 disposed on surface of heat source 64), the heat dissipating component comprising a plurality of protrusions, each of the protrusions comprising a plurality of first sections and a plurality of second sections (Fig. 10 thermal module 100 has protruding portions 104 with a curved edge and sawtooth-shaped protruding portion 102 with a slanted edge), wherein a dimension of the first sections is different from a dimension of the second sections (Fig. 10 would reasonably suggest and disclose to a person of ordinary skill in the art that the curved edge of protruding portions 104 has a different length than the slanted edge of the sawtooth-shaped protruding portion 102, see MPEP 2125.I). Chen does not appear to teach wherein a material of the protrusions of the heat dissipating component comprises graphite sheet, Si, phase change material, liquid metal paste, thermal paste, or AIN. Tangring teaches wherein a material of the protrusions of the heat dissipating component comprises graphite sheet, Si, phase change material, liquid metal paste, thermal paste, or AIN (Par. 25 teaches that “the heat dissipating structure is formed at least in places with…aluminum nitride”). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen with the teachings of Tangring because, as both Chen and Tangring present suitable materials for use in a heat dissipation structure, it would have been obvious to substitute Chen’s aluminum heat dissipation material with Tangring’s aluminum nitride heat dissipation material to achieve the predictable result of forming Chen’s thermal fins from aluminum nitride. Regarding claim 7, the combination of Chen and Tangring teaches the semiconductor structure of claim 1, wherein the first sections and the second sections are alternately and repetitively arranged (Chen fig. 10 thermal module 100 comprises and arrangement of segments of sawtooth shaped protruding portion 102 and protruding portion 104 which alternate and repeat). Regarding claim 8, the combination of Chen and Tangring teaches the semiconductor structure of claim 7, wherein each of the protrusions comprises a plurality of third sections (Fig. 10 thermal module 100 further comprises sunken portions 106 opposite protruding portions 104), wherein a dimension of the third sections is different from the dimension of the first sections and is different from the dimension of the second sections (While Chen fig. 10 appears to teach wherein the protruding portions 104 and sunken portions 106 have the same edge length dimension, Chen further teaches in par. 7 that “larger contacting area…dissipate[s] the heat generated by the heat source 44 quickly in an air cooling manner” and since the surface area of the thermal modules affects level of heat dissipation from the thermal modules, then the surface area of each of the segments of the thermal modules is a result effective variable that may be optimized by a person of ordinary skill. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Chen and Tangring such that a dimension of the third sections is different from the dimension of the first sections and is different from the dimension of the second sections, see MPEP 2144.05(II)(B)). Regarding claim 10, Chen teaches a semiconductor structure comprising: a first semiconductor substrate having a front side and a back side (Figs. 10/6 heat source 64 has front side and a back side and par. 26 teaches that “the heat source 64 can be a central processing unit or a chip installed on the circuit board 63.” Examiner notes fig. 6 illustrates details omitted in the embodiment represented in fig. 10 and so reference will be made to both figures for clarity); a second semiconductor substrate having a front side and a back side, wherein the front side of the second semiconductor substrate is bonded to the front side of the first semiconductor substrate (Figs. 10/6 circuit board 63 has a back side and a front side bonded to front side of heat source 64); and a heat dissipating component disposed on the back side of the first semiconductor substrate (Fig. 10/6 thermal module 100 disposed on back side of heat source 64), the heat dissipating component comprising a plurality of protrusions, each of the protrusions comprising a plurality of first sections and a plurality of second sections (Fig. 10 thermal module 100 has protruding portions 104 with a curved edge and sawtooth-shaped protruding portion 102 with a slanted edge), wherein a dimension of the first sections is different from a dimension of the second sections (Fig. 10 would reasonably suggest and disclose to a person of ordinary skill in the art that the curved edge of protruding portions 104 has a different length than the slanted edge of the sawtooth-shaped protruding portion 102, see MPEP 2125.I). Chen does not appear to teach wherein a material of the protrusions of the heat dissipating component comprises graphite sheet, Si, phase change material, liquid metal paste, thermal paste, or AIN. Tangring teaches wherein a material of the protrusions of the heat dissipating component comprises graphite sheet, Si, phase change material, liquid metal paste, thermal paste, or AIN (Par. 25 teaches that “the heat dissipating structure is formed at least in places with…aluminum nitride”). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen with the teachings of Tangring because, as both Chen and Tangring present suitable materials for use in a heat dissipation structure, it would have been obvious to substitute Chen’s aluminum heat dissipation material with Tangring’s aluminum nitride heat dissipation material to achieve the predictable result of forming Chen’s thermal fins from aluminum nitride. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Chen (US20100206538A1) and Tangring (US20220320404A1) as applied to claim 1 above, and further in view of Frederich et al. (US20130168255A1, hereinafter Frederich). Regarding claim 2, the combination of Chen and Tangring teaches the semiconductor structure of claim 1. The combination of Chen and Tangring does not appear to teach a liner oxide layer on the surface of the semiconductor substrate; and a seed layer on the liner oxide layer, wherein bottoms of the protrusions are interconnected by the seed layer. Frederich teaches a liner oxide layer on the surface of the semiconductor substrate (Par. 17 “deposition of an insulating dielectric layer (generally silicon oxide or silicon nitride, for example)”); and a seed layer on the liner oxide layer, wherein bottoms of the protrusions are interconnected by the seed layer (Par. 17 “deposition of a thin film of copper, called a seed layer” which allows the “filling of the vias by copper electroplating”). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Chen and Tangring with the teachings of Frederich because, as Chen is silent as to the specific construction methods of their heat dissipating structure, this would motivate a person of ordinary skill to seek out references such as Frederich who do teach a technique of forming a heat dissipation structure. Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Chen (US20100206538A1) and Tangring (US20220320404A1) as applied to claim 1 above, and further in view of Chen et al. (US20060125090A1, hereinafter Chen’090). Regarding claim 4, the combination of Chen and Tangring teaches the semiconductor structure of claim 1. bottoms of the protrusions are spaced apart from each other (Chen fig. 10 bottoms of sawtooth shaped protruding portions 102 are spaced apart from each other). The combination of Chen and Tangring does not appear to teach wherein the protrusions are directly formed on the surface of the semiconductor substrate. Chen’090 teaches wherein the protrusions are directly formed on the surface of the semiconductor substrate (Fig. 1 via stacks 30 formed directly on and embedded within substrate 20 and par. 18 teaches that “the plurality of via stacks 30 serve as good thermal paths for conducting heat away from the semiconductor device”). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Chen and Tangring with teachings from Chen’090 because as both Chen and Chen’090 teach suitable configuration for heat dissipation stacks, it would have been obvious to substitute Chen’s configuration with a stack disposed on a conductive base with Chen’090’s configuration where the stack is formed directly on and embedded within the substrate to achieve the predictable result of forming the sawtooth shaped protruding portion 102 directly on and embedded within heat source 64. Regarding claim 5, the combination of Chen, Tangring, and Chen’090 teaches the semiconductor structure of claim 4, wherein bottoms of the protrusions are embedded in the surface of the semiconductor substrate (Chen’090 teaches in fig. 1 via stacks 30 formed directly on and embedded within substrate 20 and so the combination of Chen, Tangring, and Chen’090 teaches wherein the bottommost sawtooth shaped protruding portion 102 is formed directly on and embedded within heat source 64, see above rejection of claim 4). Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Chen (US20100206538A1) and Tangring (US20220320404A1) as applied to claim 1 above, and further in view of Lee (US20110176280A1). Regarding claim 9, the combination of Chen and Tangring teaches the semiconductor structure of claim 1. The combination of Chen and Tangring does not appear to teach a via disposed in the semiconductor substrate, wherein the via is connected to one or more of the protrusions. Lee teaches a via disposed in the semiconductor substrate, wherein the via is connected to one or more of the protrusions (Par. 32 “thermal vias 16 are disposed at the upper printed circuit board 12 to function as heat paths that more rapidly transfer heat from the semiconductor chip 11 to…air”). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Chen and Tangring with the teachings of Lee because the introduction of thermal vias within a substrate provides “heat paths that more rapidly transfer heat from the semiconductor chip” (Lee par. 32). Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Chen (US20100206538A1) and Tangring (US20220320404A1) as applied to claim 10 above, and further in view of Tsai et al. (US20220359369A1, hereinafter Tsai). Regarding claim 11, the combination of Chen and Tangring teaches the semiconductor structure of claim 10. The combination of Chen and Tangring does not appear to teach a plurality of bonding pads disposed on the back side of the second semiconductor substrate. Tsai teaches a plurality of bonding pads disposed on the back side of the second semiconductor substrate (Fig. 31C substrate 170 has bonding pads 174 on front side and backside). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Chen and Tangring with the teachings of Tsai because as Chen is silent as to the integration of their device into a larger semiconductor structure, this would motivate a person of ordinary skill to seek out references such as Tsai who do explicitly teach further details of integrating a heat sink into a semiconductor device. Regarding claim 12, the combination of Chen and Tangring teaches the semiconductor structure of claim 10. The combination of Chen and Tangring does not appear to teach wherein the first semiconductor substrate is a CMOS wafer, and the second semiconductor substrate is an array wafer. Tsai teaches wherein the first semiconductor substrate is a CMOS wafer (Fig. 30C transistor structure 109 has heat sink 160 on its backside), and the second semiconductor substrate is an array wafer (Fig. 30C first substrate 170). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Chen and Tangring with the teachings of Tsai because as Chen is silent as to the integration of their device into a larger semiconductor structure, this would motivate a person of ordinary skill to seek out references such as Tsai who do explicitly teach further details of integrating a heat sink into a semiconductor device. Regarding claim 13, the combination of Chen and Tangring teaches the semiconductor structure of claim 10. The combination of Chen and Tangring does not appear to teach wherein the first semiconductor substrate is an array wafer, and the second semiconductor substrate is a CMOS wafer. Tsai teaches wherein the first semiconductor substrate is an array wafer (Fig. 31C substrate 170 has heat sink 160 on its backside), and the second semiconductor substrate is a CMOS wafer (Fig. 30C transistor structure 109). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Chen and Tangring with the teachings of Tsai because as Chen is silent as to the integration of their device into a larger semiconductor structure, this would motivate a person of ordinary skill to seek out references such as Tsai who do explicitly teach further details of integrating a heat sink into a semiconductor device. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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Prosecution Timeline

Dec 11, 2023
Application Filed
Jun 18, 2026
Non-Final Rejection mailed — §103
Aug 31, 2026
Response Filed
Oct 13, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+12.5%)
2y 10m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 139 resolved cases by this examiner. Grant probability derived from career allowance rate.

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