Prosecution Insights
Last updated: October 27, 2026

Cole Leon Lindsey, USPTO Patent Examiner

Listed by the USPTO as LINDSEY, COLE LEON

Tech Center 2800 • Art Units: 2812

This examiner grants 89% of resolved cases

Analysis

LINDSEY, COLE LEON is a USPTO patent examiner in Tech Center 2800 and Art Unit 2812. The record covers 139 resolved cases, with an 89.2% allowance rate and a median of 1044 days to allowance. The high allowance figure indicates that most matters in the record reached allowance, while the median timing still supports planning for a prosecution period extending beyond initial examination.

The interview lift is 12.5%, showing a positive association between interviews and allowance outcomes, although the effect is smaller than the overall allowance result. The listed companies are Taiwan Semiconductor Manufacturing, Samsung Electronics, and Intel. The listed firms are Fish & Richardson, Birch Stewart Kolasch & Birch, and Crowell. Claim-focused interviews may complement an already favorable allowance environment.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

89.2%
Allow Rate
+21.2% vs TC avg
170
Total Applications
+12.5%
Interview Lift
1044
Avg Prosecution Days
Based on 139 resolved cases, 2023–2026

Rejection Statute Breakdown

0.2%
§101 Eligibility
29.6%
§102 Novelty
53.3%
§103 Obviousness
15.4%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18765816 SEMICONDUCTOR PACKAGE Non-Final OA SAMSUNG ELECTRONICS CO., LTD.
18626727 SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR PACKAGE WITH CAPACITOR EMBEDDED IN DIELECTRIC LAYER Non-Final OA SAMSUNG ELECTRONICS CO., LTD.
18420969 SEMICONDUCTOR DEVICE INCLUDING ACTIVE PATTERN Non-Final OA SAMSUNG ELECTRONICS CO., LTD.
18090807 INTEGRATED CIRCUIT STRUCTURES HAVING LAYER SELECT TRANSISTORS FOR SHARED PERIPHERALS IN MEMORY Non-Final OA Intel Corporation
18087517 UNDER BUMP METALLIZATIONS, SOLDER COMPOSITIONS, AND STRUCTURES FOR DIE INTERCONNECTS ON INTEGRATED CIRCUIT PACKAGING Final Rejection Intel Corporation
18589721 STITCH BOND TO COPPER NANOTWIN PLATED LEAD Non-Final OA Texas Instruments Incorporated
18138811 METHOD OF PLASMA CLEANING OF FUSED SILICA TUBES Final Rejection Applied Materials, Inc.
18124674 MULTI-VT INTEGRATION SCHEME FOR SEMICONDUCTOR DEVICES Non-Final OA Applied Materials, Inc.
18787573 PASSIVATION LAYERS WITH ROUNDED CORNERS Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18781361 SEMICONDUCTOR STRUCTURE HAVING SEAM SEALED Final Rejection TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
18760276 SEMICONDUCTOR DEVICE AND METHODS OF FORMATION Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18644188 SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME Non-Final OA TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
18786265 Wafer Bonding Apparatus and Method Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18515472 PACKAGING STRUCTURE AND PACKAGING METHOD Non-Final OA Semiconductor Manufacturing International (Shanghai) Corporation

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Frequently Asked Questions

What is examiner Cole Leon Lindsey's allowance rate?

89.2% of resolved applications examined by Cole Leon Lindsey were allowed (139 resolved cases), compared with 82.1% across Art Unit 2812 over the last five years.

Does an interview help with examiner Cole Leon Lindsey?

This examiner's interview lift is +12.5 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.

How long does examiner Cole Leon Lindsey take to allow a patent?

Applications allowed by Cole Leon Lindsey took 1,044 days on average from filing to allowance.

Which art unit does examiner Cole Leon Lindsey work in?

Cole Leon Lindsey examines applications in Art Unit 2812 in Tech Center 2800 (Semiconductors, Circuits & Optics).

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