Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 04/11/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US20100206538A1).
Regarding claim 1, Chen discloses a semiconductor structure comprising:
a semiconductor substrate (Fig. 4 heat source 64 which par. 26 teaches “can be a central processing unit or a chip”); and
a heat dissipating component disposed on a surface of the semiconductor substrate (Fig. 4 thermal fins 46), the heat dissipating component comprising a plurality of protrusions, each of the protrusions comprising a plurality of first sections and a plurality of second sections, wherein a dimension of the first sections is different from a dimension of the second sections (Fig. 4 see plurality of protruding parts 463 and parts that are not protruding from thermal fin 46 which have different lateral dimensions).
Regarding claim 7, Chen discloses the semiconductor structure of claim 1,
wherein the first sections and the second sections are alternately and repetitively arranged (Fig. 4 plurality of protruding parts 463 and parts that are not protruding from thermal fin 46 which have different lateral dimensions are alternately and repetitively arranged).
Regarding claim 10, Chen discloses a semiconductor structure comprising:
a first semiconductor substrate having a front side and a back side (Fig. 6 heat source 64 has front side down and back side up);
a second semiconductor substrate having a front side and a back side, wherein the front side of the second semiconductor substrate is bonded to the front side of the first semiconductor substrate (Fig. 6 circuit board 63 has back side down and front side up, and the front side is bonded to the front side of heat source 64); and
a heat dissipating component disposed on the back side of the first semiconductor substrate (Fig. 6 thermal fins 66), the heat dissipating component comprising a plurality of protrusions, each of the protrusions comprising a plurality of first sections and a plurality of second sections, wherein a dimension of the first sections is different from a dimension of the second sections (Fig. 6 see plurality of protruding parts 663 and parts that are not protruding from thermal fin 66 which have different lateral dimensions).
Claims 1 and 4-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsushima et al. (US20130284404A1, hereinafter Matsushima).
Regarding claim 1, Matsushima discloses a semiconductor structure comprising:
a semiconductor substrate (Fig. 4 substrate 11); and
a heat dissipating component disposed on a surface of the semiconductor substrate (Fig. 4 fin 13 disposed within and on surface of substrate 11), the heat dissipating component comprising a plurality of protrusions, each of the protrusions comprising a plurality of first sections and a plurality of second sections (Fig. 4 fin 13 has convex portions 14 and portions that are not convex), wherein a dimension of the first sections is different from a dimension of the second sections (Fig. 4 convex portion 14 has a different dimension than the portions that are not convex).
Regarding claim 4, Matsushima discloses the semiconductor structure of claim 1,
wherein the protrusions are directly formed on the surface of the semiconductor substrate (Fig. 4 fin 13 is directly formed on substrate 11 and so the portions that are not convex are directly formed on its surface), and bottoms of the protrusions are spaced apart from each other (Fig. 5 see plurality of bottoms of fins 13 spaced apart from each other).
Regarding claim 5, Matsushima discloses the semiconductor structure of claim 4,
wherein bottoms of the protrusions are embedded in the surface of the semiconductor substrate (Fig. 4 portions of fin 13 that are not convex are embedded in the surface of substrate 11).
Regarding claim 6, Matsushima discloses the semiconductor structure of claim 4,
wherein a material of the protrusions of the heat dissipating component comprises graphite sheet, Si, phase change material, liquid metal paste, thermal pad, thermal paste, or AIN (Par. 47 “the pin-shaped fins 13…may be made of copper” and so convex portions 14 of fins 13 would constitute a thermal pad).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US20100206538A1) in view of Frederich et al. (US20130168255A1, hereinafter Frederich).
Regarding claim 2, Chen teaches the semiconductor structure of claim 1, further comprising:
Chen does not appear to teach
a liner oxide layer on the surface of the semiconductor substrate; and
a seed layer on the liner oxide layer, wherein bottoms of the protrusions are interconnected by the seed layer.
Frederich teaches
a liner oxide layer on the surface of the semiconductor substrate (Par. 17 “deposition of an insulating dielectric layer (generally silicon oxide or silicon nitride, for example)”; and
a seed layer on the liner oxide layer, wherein bottoms of the protrusions are interconnected by the seed layer (Par. 17 “deposition of a thin film of copper, called a seed layer” which allows the “filling of the vias by copper electroplating”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen with the teachings of Frederich because as Chen is silent as to the specific construction of their copper pillars, this would motivate a person of ordinary skill in the art to seek out references such as Frederich who explicitly disclose a method of creating a copper pillar.
Regarding claim 3, The combination of Chen and Frederich teaches the semiconductor structure of claim 2,
wherein a material of the protrusions of the heat dissipating component comprises Ag, Cu, Au, Al, or W (Chen Par. 26 “The conductive base 62 and the plurality of thermal fins 66 can be made of metal material, such as copper”).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US20100206538A1).
Regarding claim 8, Chen teaches the semiconductor structure of claim 7,
wherein each of the protrusions comprises a plurality of third sections, wherein a dimension of the third sections is different from the dimension of the first sections and is different from the dimension of the second sections (Chen par. 5 teaches that “increasing contacting area between the thermal device 20 and the air” then “the heat generated by the heat source 24 can be dissipated by the thermal fins 26 effectively.” Therefore, as the surface area affects the heat dissipated by the thermal device, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B)). While Chen does not explicitly teach a plurality of third sections, the primary function of the protrusions 463 is to increase surface area, see Chen pars. 5-6. A duplication of a protrusion 463 to form a plurality of third sections would not provide any new or unexpected results as the primary function of increasing surface area is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate protrusions 463 with dimensions optimized by a person of ordinary skill to form a plurality of third sections on fins 46 see MPEP 2144.04(VI)(B)).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US20100206538A1) in view of Lee (US20110176280A1).
Regarding claim 9, Chen teaches the semiconductor structure of claim 1.
Chen does not appear to teach
a via disposed in the semiconductor substrate, wherein the via is connected to one or more of the protrusions
Lee teaches
a via disposed in the semiconductor substrate, wherein the via is connected to one or more of the protrusions (Par. 32 “thermal vias 16 are disposed at the upper printed circuit board 12 to function as heat paths that more rapidly transfer heat from the semiconductor chip 11 to…air”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen with the teachings of Lee because the introduction of thermal vias within a substrate provides “heat paths that more rapidly transfer heat from the semiconductor chip 11 to…air” (Lee par. 32).
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US20100206538A1) in view of Tsai et al. (US20220359369A1, hereinafter Tsai).
Regarding claim 11, Chen teaches the semiconductor structure of claim 10.
Chen does not appear to teach
a plurality of bonding pads disposed on the back side of the second semiconductor substrate.
Tsai teaches
a plurality of bonding pads disposed on the back side of the second semiconductor substrate (Fig. 31C substrate 170 has bonding pads 174 on frontside and backside).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen with the teachings of Tsai because as Chen is silent as to the bonding methods between this different substrates, this would motivate a person of ordinary skill in the art to seek out references such as Tsai who explicitly teach methods such as the use of bonding pads.
Regarding claim 12, Chen teaches the semiconductor structure of claim 10.
Chen does not appear to teach
wherein the first semiconductor substrate is a CMOS wafer, and the second semiconductor substrate is an array wafer.
Tsai teaches
wherein the first semiconductor substrate is a CMOS wafer (Fig. 30C transistor structure 109 has heat sink 160 on its backside), and the second semiconductor substrate is an array wafer (Fig. 30C first substrate 170).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen with the teachings of Tsai because as Chen is silent as to the integration of their device into a larger semiconductor structure, this would motivate a person of ordinary skill to seek out references such as Tsai who do explicitly teach the integration of a heat sink into a semiconductor device.
Regarding claim 13, Chen teaches the semiconductor structure of claim 10.
Chen does not appear to teach
wherein the first semiconductor substrate is an array wafer, and the second semiconductor substrate is a CMOS wafer.
Tsai teaches
wherein the first semiconductor substrate is an array wafer (Fig. 31C substrate 170 has heat sink 160 on its backside), and the second semiconductor substrate is a CMOS wafer (Fig. 30C transistor structure 109).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen with the teachings of Tsai because as Chen is silent as to the integration of their device into a larger semiconductor structure, this would motivate a person of ordinary skill to seek out references such as Tsai who do explicitly teach the integration of a heat sink into a semiconductor device.
Conclusion
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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