Prosecution Insights
Last updated: May 29, 2026
Application No. 18/534,863

STRUCTURE WITH FERROELECTRIC MEMORY STACKS HAVING DIFFERENT SWITCHING VOLTAGES AND RELATED METHODS

Non-Final OA §102§103
Filed
Dec 11, 2023
Examiner
YEMELYANOV, DMITRIY
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Globalfoundries Dresden Module One Limited Liability Company & Co. Kg
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
401 granted / 546 resolved
+5.4% vs TC avg
Strong +19% interview lift
Without
With
+18.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
35 currently pending
Career history
593
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
88.7%
+48.7% vs TC avg
§102
8.4%
-31.6% vs TC avg
§112
2.5%
-37.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 546 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I, Species IA (Fig. 3; Claims 1-3, 5, 6, 8-11 and 13) in the reply filed on 04/15/2026 is acknowledged. Claim 6 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Invention I, Species IC (“the first ferroelectric memory stack and the second ferroelectric memory stack are each within a respective metal wiring layer above the substrate.“ (Fig. 6) [0039 of PGPub), there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on . Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “ the first ferroelectric memory stack is on a device layer, and wherein the second ferroelectric memory stack is within a metal wiring layer over the device layer.” Of Claim 5. “a metal wiring layer” of Claim 9 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 5 is/are rejected under 35 U.S.C. 102(A1) as being anticipated by Slesazeck et al. (US 2017/0162250 A1). Regarding Claim 1, Slesazeck (Fig. 3) discloses a structure comprising: a first ferroelectric memory stack (c2) over a substrate (108), the first ferroelectric memory stack having a first switching voltage (VC1=V (C1+C2)/C1); and a second ferroelectric memory stack (C1) serially coupled to the first ferroelectric memory stack (C2) over the substrate (109), the second ferroelectric memory stack having a second switching voltage (“VC2=V (C1+C2)/C2) different from the first switching voltage. (“Upon further increase of the applied voltage V, also the coercive voltage of C2 will reached) [0058] Regarding Claim 5, Slesazeck discloses the structure of claim 1, wherein the first ferroelectric memory stack (303) is on a device layer (101, 102), and wherein the second ferroelectric memory stack. (304) is within a metal wiring layer (layer of 304) over the device layer. (101, 102) Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Slesazeck et al. (US 2017/0162250 A1) in view of Chen et al. (US 2023/0403863 A1). Regarding Claim 2,. Slesazeck (Fig. 3) discloses the structure of claim 1, wherein the first ferroelectric memory stack (C2) includes a first ferroelectric layer (303a), and the second ferroelectric memory stack (C1) includes a second ferroelectric layer (304a). Slesazeck further discloses materials for ferroelectric layers a different material composition from the first ferroelectric layer. (“ the ferroelectric material may comprise any of HfO.sub.2, ZrO.sub.2, any ratio of Hf and Zr combined with oxygen (e.g., Zr.sub.xHf.sub.1-xO.sub.2, where x<1) as well as any combinations thereof.”) [0028] Slesazeck does not explicitly disclose a second ferroelectric layer having a different material composition from the first ferroelectric layer. Chen (Fig. 4) discloses a second ferroelectric layer (114,the ferroelectric material includes hafnium zirconium oxide (HfZrO) among limited number of other materials) having a different material composition from the first ferroelectric layer (414 hafnium oxide (HfO.sub.2), among limited number of other materials). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure in Slesazeck in view of Chen such that a second ferroelectric layer having a different material composition from the first ferroelectric layer in order to since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (See MPEP 2144.07) and to have different polarization states which result in four different threshold voltages of the memory cell transistor [0058 Hartner] Regarding Claim 3, Slesazeck in view of Chen discloses the structure of claim 2, wherein the first ferroelectric layer includes hafnium oxide (HfO.sub.2) (414 hafnium oxide (HfO.sub.2)” Chen) and the second ferroelectric layer includes hafnium-zirconium oxide (HZO). (“114, the ferroelectric material includes hafnium zirconium oxide (HfZrO)” Chen) Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Slesazeck et al. (US 2017/0162250 A1) in view of Banerjee et al. (“Hafnium Oxide (HfO2) – A Multifunctional Oxide: A Review on the Prospect and Challenges of Hafnium Oxide in Resistive Switching and Ferroelectric Memories” Small Volume 18, Issue 23 Jun 2022; Published in 05 May 2022). Regarding Claim 8, Slesazeck discloses the structure of claim 1, wherein a magnitude of the first switching voltage and a magnitude of the second switching [0052, 0058]. Slesazeck further discloses materials for ferroelectric layers a different material composition from the first ferroelectric layer. (“the ferroelectric material may comprise any of HfO.sub.2, ZrO.sub.2, any ratio of Hf and Zr combined with oxygen (e.g., Zr.sub.xHf.sub.1-xO.sub.2, where x<1) as well as any combinations thereof.”) [0028] and differences between a magnitude of the first switching voltage and a magnitude of the second switching [0052] Slesazeck does not explicitly disclose a magnitude of the first switching voltage is approximately two volts (V) and a magnitude of the second switching voltage is approximately four V. Banerjee discloses a magnitude of the second switching voltage of HfO is dependent on thickness of the layer is approximately 1.5V It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure in Slesazeck in view of Banerjee to select material thickness for ferroelectric layers such that a magnitude of the first switching voltage is approximately two volts (V) and a magnitude of the second switching voltage is approximately four V since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 276 (CCPA 1980). Allowable Subject Matter Claims 9-11 and 13 are allowable. The following is an examiner's statement of reasons for allowance: With regards to claim 9, none of the prior art teaches or suggests, alone or in combination, “a second conductive plate within the metal wiring layer, a second ferroelectric layer on the second conductive plate, and a third conductive plate on the second ferroelectric layer, wherein the second ferroelectric memory stack has a second switching voltage different from the first switching voltage such that a first bit stored within the second ferroelectric memory stack is independently adjustable relative to a second bit stored within the second ferroelectric memory stack” in the combination required by the claim. Claims 10-11 and 13 are allowed by virtue of their dependency on the independent claim 9. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance." Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DMITRIY YEMELYANOV/Examiner, Art Unit 2891
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Prosecution Timeline

Dec 11, 2023
Application Filed
May 20, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
92%
With Interview (+18.6%)
2y 7m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 546 resolved cases by this examiner. Grant probability derived from career allowance rate.

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