DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 13-24 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15-20 and 22-28 of copending Application No. 18/533,653. Although the claims at issue are not identical, they are not patentably distinct from each other because:
In regards to claim 13, 18/533,653 (claims 15, 16, 17) discloses a power module, comprising: a first circuit carrier; and at least one second circuit carrier, wherein the first circuit carrier has a plurality of power conductor structures arranged on an electrically insulating layer on a first side, the power conductor structures of the first circuit carrier forming a first power level in which external contact regions of the power conductor structures are arranged, wherein the at least one second circuit carrier is arranged spatially in parallel with the first circuit carrier, and has at least one further power conductor structure arranged on an electrically insulating layer on a first side facing the first side of the first circuit carrier, the at least one further power conductor structure of the at least one second circuit carrier forming a second power level, wherein the at least one further power conductor structure of the at least one second circuit carrier is electrically connected at an internal contact region to an internal contact region of one of the power conductor structures of the first circuit carrier, wherein at least one control signal conductor structure is arranged on the electrically insulating layer on a second side of the at least one second circuit carrier, and forms a signal level, wherein at least two semiconductor switches are arranged and electrically contacted with power connections of the at least two semiconductor switches between the conductor structures of the first power level of the first circuit carrier and the at least one further power conductor structure of the second power level of the at least one second circuit carrier, wherein control connections of the at least two semiconductor switches are electrically connected to the at least one control signal conductor structure of the at least one second circuit carrier.
In regards to claim 14, 18/533,653 (claim 18) discloses wherein the first circuit carrier has at least one thermal interface on a second side, wherein the thermal interface can be contacted with a cooling device.
In regards to claim 15, 18/533,653 (claims 19, 20) discloses wherein an encasement completely encloses the power module with the at least one thermal interface being left exposed, the encasement having at least one recess in a region of external contact regions of the first circuit carrier and in a region of external contact regions of the at least one second circuit carrier.
In regards to claim 16, 18/533,653 (claim 15) discloses wherein a common conductor structure is arranged on the electrically insulating layer as part of the signal level on the second side of the at least one second circuit carrier, control connections of the at least two semiconductor switches configured as Kelvin source connections being electrically connected to the common conductor structure.
In regards to claim 13, 18/533,653 (claim 15) discloses wherein the at least one second circuit carrier is placed in such a way that a first electrically symmetrical current star point of the signal level, which corresponds to a geometric center of the common conductor structure, overlaps at least partially with a spacer element which forms a second electrically symmetrical current star point of the first and second power levels and electrically connects the internal contact region of the at least one further power conductor structure of the at least one second circuit carrier to the internal contact region of one of the power conductor structures of the first circuit carrier.
In regards to claim 18, 18/533,653 (claim 22) discloses wherein, on the second side of the at least one second circuit carrier, at least one measuring signal conductor structure is arranged on the electrically insulating layer as part of the signal level.
In regards to claim 19, 18/533,653 (claim 23) discloses wherein an internal contact region of a first measuring signal conductor structure of the at least one second circuit carrier is electrically connected to one of the power conductor structures of the first circuit carrier via a connection line, an external contact region of the first measurement signal structure of the at least one second circuit carrier providing a power measurement point via a spacer element.
In regards to claim 20, 18/533,653 (claim 24) discloses wherein an internal contact region of a second measuring signal conductor structure of the at least one second circuit carrier is electrically connected to a first connection of a temperature sensor, a second connection of the temperature sensor being electrically connected to an internal contact region of the common conductor structure of the at least one second circuit carrier, an external contact region of the second measurement signal structure providing a temperature measurement signal.
In regards to claim 21, 18/533,653 (claim 25) discloses wherein at least one first power conductor structure of the power conductor structures of the first circuit carrier can be contacted via at least one external contact region with a positive supply connection, and at least one second power conductor structure of the power conductors of the first circuit carrier can be contacted via at least one external contact region with a negative supply connection, and at least one third power conductor structure of the power conductor structures of the first circuit carrier can be contacted via at least one external contact region with a load connection.
In regards to claim 22, 18/533,653 (claim 26) discloses wherein each of the at least two semiconductor switches forms a “high-side switch” of the power module and are arranged and electrically contacted with the power connections thereof between the at least one first power conductor structure of the first circuit carrier and the at least one further power conductor structure of the second circuit carrier, control connections of the high-side switches configured as gate connections each being electrically connected to the control signal conductor structure of the second circuit carrier the at least one further power conductor structure of the second circuit carrier being electrically connected at the internal contact region to the internal contact region of the third power conductor structure of the first circuit carrier.
In regards to claim 23, 18/533,653 (claim 27) discloses wherein, the at least two semiconductor switches each forms a “low-side switch” of the power module and are electrically arranged and electrically contacted with the power connections thereof between the at least one second conductor structure of the first circuit carrier and at least one further power conductor structure of a further second circuit carrier, control connections of the low-side switches configured as gate connections each being electrically connected to a control signal conductor structure of the further second circuit carrier, the at least one further power conductor structure of the further second circuit carrier being electrically connected at an internal contact region to the internal contact region of the second power conductor structure of the first circuit carrier.
In regards to claim 24, 18/533,653 (claim 28) discloses wherein the first circuit carrier and/or the at least one second circuit carrier is an active metal braze (AMB) substrate or a direct bonded copper (DBC) substrate.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 February 5, 2026