DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I claims 1-16 in the reply filed on 24 April 2026 is acknowledged. The traversal is on the ground(s) that there would be no undo search burden. This is not found persuasive because a search directed to the device of Group I would require different classification areas as well as search terms than the search directed to the method of Group II, as described in the restriction requirement with a mail date of March 6, 2026.
The requirement is still deemed proper and is therefore made FINAL.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 8, and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 of U.S. Patent No. 12,341,077. Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding claim 1, claim 1 of U.S. Patent No. 12,341,077 teaches a semiconductor substrate with an original semiconductor surface; a circuit element (active region) within a body region of the semiconductor substrate, a horizontal heat dissipation plate in the semiconductor substrate and under the circuit element; wherein the horizontal heat dissipation plate comprises a first thermal dissipation material with a first thermal conductivity higher than the thermal conductivity of the semiconductor substrate or the thermal conductivity of silicon oxide.
Regarding claim 8, claim 2 of U.S. Patent No. 12,341,077 teaches the heat dissipation substrate includes a thermal via or a heat sink connected to the horizontal heat dissipation plate.
Regarding claim 14, claim 7 of U.S. Patent No. 12,341,077 teaches further comprising a vertical heat dissipation column in the semiconductor substrate and surrounding the circuit element; wherein the horizontal heat dissipation plate is connected to the vertical heat dissipation column (Fig. 16, 306 vertical or thickness portions), and the vertical heat dissipation column comprises a second thermal dissipation material with a second thermal conductivity higher than the thermal conductivity of the semiconductor substrate or the thermal conductivity of silicon oxide.
Claims 1, 4, 8, 10, are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 12,341,076. Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding claim 1, claims 1 and 21 of U.S. Patent No. 12,341,076 teach a semiconductor substrate with an original semiconductor surface; a circuit element (active region) within a body region of the semiconductor substrate, a horizontal heat dissipation plate in the semiconductor substrate and under the circuit element; wherein the horizontal heat dissipation plate comprises a first thermal dissipation material with a first thermal conductivity higher than the thermal conductivity of the semiconductor substrate or the thermal conductivity of silicon oxide..
Regarding claim 4, claim 20 of U.S. Patent No. 12,341,076 teaches the limitations of claim 4.
Regarding claim 8, claims 14 and 15 of U.S. Patent No. 12,341,076 teach the limitations of claim 8.
Regarding claim 9, claims 1 and 21 of U.S. Patent No. 12,341,076 teach the limitations of claim 9.
Regarding claim 10, claims 1 and 21 of U.S. Patent No. 12,341,076 teach the limitations of claim 10.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 7-10, 12, 14-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hammond (US Publication 20260075939).
Regarding claim 1, Hammond teaches a device structure, comprising:
a semiconductor substrate with an original semiconductor surface (Fig. 16, 302);
a circuit element located within a semiconductor body region of the semiconductor substrate (Fig. 16, 310); and
a horizontal heat dissipation plate in the semiconductor substrate and under the circuit element (Fig. 16, 306);
wherein the horizontal heat dissipation plate comprises a first thermal dissipation material with a first thermal conductivity higher than the thermal conductivity of the semiconductor substrate or the thermal conductivity of silicon oxide (para 96, 302 material "e.g. silicon", para 99, 306 material "including but not limited to silicon, germanium, and III-V semiconductors", III-V semiconductors have thermal conductivity higher than silicon oxide).
Regarding claim 2, Hammond teaches the limitations of claim 1 upon which claim 2 depends.
Hammond teaches wherein the first thermal dissipation material is BN, AIN, or metal (para 99, 302 materials III-V semiconductors including BN and AIN).
Regarding claim 3, Hammond teaches the limitations of claim 2 upon which claim 3 depends.
Hammond teaches wherein the horizontal heat dissipation plate further comprises a thin oxide layer covering the first thermal dissipation material (Fig. 16, 316).
Regarding claim 7, Hammond teaches the limitations of claim 1 upon which claim 7 depends.
Hammond teaches wherein a heat-dissipation substrate is connected to the horizontal heat dissipation plate through an opening under the horizontal heat dissipation plate (Fig, 16, 304 connected to 306).
Regarding claim 8, Hammond teaches the limitations of claim 7 upon which claim 8 depends.
Hammond teaches wherein the heat-dissipation substrate includes a thermal via or a heat sink connected to the horizontal heat dissipation plate (Fig. 16, 342, para 121).
Regarding claim 9, Hammond teaches the limitations of claim 1 upon which claim 9 depends.
Hammond teaches wherein the circuit element is a transistor, a resistor, a capacitor, a diode, or an inductor (para 96, 310 transistor).
Regarding claim 10, Hammond teaches the limitations of claim 1 upon which claim 10 depends.
Hammond teaches wherein the circuit element is a transistor which comprises a source region, a drain region and a channel region, the horizontal heat dissipation plate is connected to a bottom surface of the source region and a bottom surface of the drain region (Fig. 16, transistor 310, source/drain 314a/b, channel 325, 306 connected to bottom of 314a/b).
Regarding claim 12, Hammond teaches the limitations of claim 10 upon which claim 12 depends.
Hammond teaches wherein a first PN junction is existed between the source region and the channel region, and a second PN junction is existed between the drain region and the channel region, and both the first PN junction and the second PN junction are right above the horizontal heat dissipation plate (Fig. 16, PN junctions on either side of the channel region 325 right above 306).
Regarding claim 14, Hammond teaches the limitations of claim 1 upon which claim 14 depends.
Hammond teaches further comprising a vertical heat dissipation column in the semiconductor substrate and surrounding the circuit element; wherein the horizontal heat dissipation plate is connected to the vertical heat dissipation column (Fig. 16, 306 vertical or thickness portions), and the vertical heat dissipation column comprises a second thermal dissipation material with a second thermal conductivity higher than the thermal conductivity of the semiconductor substrate or the thermal conductivity of silicon oxide (para 96, 302 material "e.g. silicon", para 99, 306 material "including but not limited to silicon, germanium, and III-V semiconductors", III-V semiconductors have thermal conductivity higher than silicon oxide).
Regarding claim 15, Hammond teaches the limitations of claim 14 upon which claim 15 depends.
Hammond teaches wherein the semiconductor substrate comprises an edge region remote from the circuit element, and the vertical heat dissipation column extends from the circuit element to a position close to the edge region of the semiconductor substrate (Fig. 16, vertical or thickness portion of 306 extends to edge region).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6, 11, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Hammond (US Publication 20260075939) in view of Gambino et al (US Publication 20150084128).
Regarding claim 4, Hammond teaches the limitations of claim 1 upon which claim 4 depends.
Hammond does not specifically teach a shallow trench isolation (STI) region surrounding the semiconductor body region, and the horizontal heat dissipation plate extends outward to the STI region.
Gambino teaches a shallow trench isolation (STI) region surrounding the semiconductor body region, and the horizontal heat dissipation plate extends outward to the STI region (Fig. 31B, 105, para 84, on either side of active region where horizontal portion of 122 extends outward to 105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Hammond to include the STI region as taught by Gambino in order to further improve the reliability and operability of the device.
Regarding claim 5, Hammond as modified teaches the limitations of claim 4 upon which claim 5 depends.
Hammond teaches wherein the semiconductor substrate comprises an edge region remote from the circuit element, and the horizontal heat dissipation plate further extends close to the edge region of the semiconductor substrate (Fig. 16, edges of 302 and 306).
Regarding claim 6, Hammond as modified teaches the limitations of claim 5 upon which claim 6 depends.
Hammond teaches wherein a heat-dissipation sink is connected to the horizontal heat dissipation plate close to the edge region of the semiconductor substrate through an opening above the horizontal heat dissipation plate (Fig, 16, 304 connected to 306).
Regarding claim 11, Hammond as modified teaches the limitations of claim 4 upon which claim 11 depends.
Hammond does not specifically teach wherein the horizontal heat dissipation plate comprises a first horizontal heat dissipation plate and a second horizontal heat dissipation plate, there is a gap between the first horizontal heat dissipation plate and the second horizontal heat dissipation plate, and the gap is right under the channel region of the transistor.
Gambino teaches wherein the horizontal heat dissipation plate comprises a first horizontal heat dissipation plate and a second horizontal heat dissipation plate, there is a gap between the first horizontal heat dissipation plate and the second horizontal heat dissipation plate, and the gap is right under the channel region of the transistor (Fig. 1A, gap between 120 under 131).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Hammond to include the horizontal heat dissipation plate comprises a first horizontal heat dissipation plate and a second horizontal heat dissipation plate, there is a gap between the first horizontal heat dissipation plate and the second horizontal heat dissipation plate, and the gap is right under the channel region of the transistor as taught by Gambino in order to further improve the thermal management properties of the device.
Regarding claim 16, Hammond as modified teaches the limitations of claim 14 upon which claim 16 depends.
Hammond does not specifically teach further comprising a shallow trench isolation (STI) region surrounding the semiconductor body region, wherein the vertical heat dissipation column is within the STI region.
Gambino teaches further comprising a shallow trench isolation (STI) region surrounding the semiconductor body region, wherein the vertical heat dissipation column is within the STI region (Fig. 31B, 105, para 84, on either side of active region where horizontal portion of 122 extends outward to 105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Hammond to include the STI region as taught by Gambino in order to further improve the reliability and operability of the device.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hammond (US Publication 20260075939) in view of Lee et al (US Publication 20190326324).
Regarding claim 13, Hammond teaches the limitations of claim 10 upon which claim 13 depends.
Hammond does not specifically teach wherein the transistor is a fin-structured transistor, and a fin width of the fin-structured transistor is substantially the same as a width of the horizontal heat dissipation plate right under the fin- structured transistor.
Lee teaches wherein the transistor is a fin-structured transistor, and a fin width of the fin-structured transistor is substantially the same as a width of the horizontal heat dissipation plate right under the fin- structured transistor (Fig. 9, fin 101 width substantially the same as heat conducting dielectric 104 directly under 101).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Hammond to include the fin width and horizontal heat dissipation plate width are substantially the same as taught by Lee in order to prevent sharp material boundaries and minimize contact thermal resistance within the device, creating a safer and more functional device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Botula et al (US Patent 9530711) – Silicon-on-insulator heat sink.
Yu et al (US Patent 12272616) – Heat-dissipating structures for semiconductor devices and methods of manufacture.
Botula et al (US Publication 20200027973) – Integrated circuit heat dissipation using nanostructures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571 272 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
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