DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 16-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/11/2026.
Applicant’s election without traverse of claims 1-15 in the reply filed on 06/11/2026 is acknowledged in the action below.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/11/2023 is being considered by the examiner.
Drawings
The drawings submitted on 12/11/2023 are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 20220328496 A1) in view of Chan et al. (US 20220093734 A1).
Regarding claim 1, Kang discloses a semiconductor device, comprising:
a substrate (100) including an active pattern (AP1/AP2) that is defined by a trench (TR); ([0045], Fig. 5A-5E)
a device isolation layer (ST) in the trench (TR); ([0046], Fig. 5A-5E)
a first source/drain pattern (SD1) and a second source/drain pattern (SD2) that are on the active pattern (AP1/AP2); ([0050], Fig. 5A-5E)
a gate cutting pattern (CT) that are on the device isolation layer (ST); and
a gate spacer (GS) on a side surface of the gate cutting pattern (CT), ([0072], Fig. 5A-5E)
a first thickness of the lower portion of the gate spacer (GS) is different from a second thickness of an upper portion of the gate spacer (GS). (Fig. 5A)
Kang does not disclose:
a partition wall between the first and second source/drain patterns;
a dam structure,
wherein the first source/drain pattern is in a recess between the partition wall and the dam structure,
a lower portion of the gate spacer is interposed between the dam structure and the gate cutting pattern
However, Chan discloses:
a partition wall (46) between the first and second source/drain patterns (50); ([0105], Fig. 2i)
a dam structure (41),
wherein the first source/drain pattern (50) is in a recess between the partition wall (46) and the dam structure (41), (Fig. 2h-2i)
a lower portion of the gate spacer (41) is interposed between the dam structure (46) and the gate cutting pattern (27).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kang and Chan to have a partition wall between the first and second source/drain patterns; a dam structure, wherein the first source/drain pattern is in a recess between the partition wall and the dam structure, a lower portion of the gate spacer is interposed between the dam structure and the gate cutting pattern in order to “reduce a capacitive coupling between the source/drain regions and the gate (Chan, [0003] as well as “serve an additional purpose of masking the source/drain regions from the etching.” (Chan, [0004])
Regarding claim 2, Kang discloses the semiconductor device of claim 1, wherein the first thickness is larger than the second thickness. (Fig. 5A)
Regarding claim 3, Chan discloses the semiconductor device of claim 1, wherein the first source/drain pattern (50) comprises a first side surface (right) and a second side surface (left), which are opposite to each other,
the first side surface (right) is in contact with the partition wall (46), and
the second side surface (left) is in contact with the dam structure (41). (Fig. 2i)
Regarding claim 4, Kang discloses the semiconductor device of claim 1, further comprising:
a first channel pattern (CH1) and a second channel pattern (CH2) that are on the active pattern (AP1/AP2); and
a gate electrode (GE) on the first and second channel patterns (CH1/CH2),
and the gate cutting pattern (CT) extends into the gate electrode (GE). (Fig. 5A)
Kang does not disclose:
wherein the partition wall is interposed between the first and second channel patterns,
However, Chan discloses:
wherein the partition wall (46) is interposed between the first and second channel patterns (20/21). (Fig. 1b)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kang and Chan for similar reasons mentioned beforehand.
Regarding claim 5, Chan discloses the semiconductor device of claim 4, wherein the first channel pattern (20) comprises a plurality of semiconductor patterns (24), which are spaced apart from each other in a stack (20),
each of the semiconductor patterns (24) has a first side surface (right) and a second side surface (left), which are opposite to each other,
the first side surface (right) is connected to the partition wall (46), and
the gate cutting pattern (27) is on the second side surface (left). (Fig. 1a and 1b)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kang and Chan for similar reasons mentioned beforehand.
Regarding claim 6, Chan discloses the semiconductor device of claim 5, further comprising a gate insulating layer (41) between the semiconductor patterns (24) and the gate electrode (30),
wherein the gate insulating layer (41) is interposed between the second side surface and the gate cutting pattern (27). (Fig. 2c)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kang and Chan for similar reasons mentioned beforehand.
Regarding claim 11, Kang discloses a semiconductor device, comprising:
a substrate (100) including an active pattern (AP1/AP2) that is defined by a trench (TR); ([0045], Fig. 5A-5E)
a device isolation layer (ST) in the trench (TR); ([0046], Fig. 5A-5E)
a first channel pattern (CH1) and a second channel pattern (CH2) that are on the active pattern (AP1/AP2); ([0048], Fig. 5A-5E)
a gate electrode (GE) on the first and second channel patterns (CH1/CH2); ([0063], Fig. 5A-5E) and
a gate cutting pattern (CT) on the device isolation layer (ST), ([0068], Fig. 5A-5E)
wherein the gate cutting pattern (CT) extends into the gate electrode (GE), (Fig. 5A)
the first channel pattern (CH1) comprises a plurality of semiconductor patterns (SP1-SP3), which are spaced apart from each other in a stack, (Fig. 5A-5E)
each of the semiconductor patterns (SP1-SP3) has a first side surface and a second side surface, which are opposite to each other,
Kang does not disclose:
a partition wall between the first and second channel patterns;
the first side surface is connected to the partition wall, and
the gate cutting pattern is on the second side surface.
However, Chan discloses:
a partition wall (46) between the first and second channel patterns (20/21); ([0075], Fig. 1a-1b)
the first side surface (right of the first channel pattern 20) is connected to the partition wall (46), and
the gate cutting pattern (27) is on the second side surface (left). (Fig. 1a-1b)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kang and Chan for a partition wall between the first and second channel patterns; the first side surface is connected to the partition wall, and the gate cutting pattern is on the second side surface in order to “reduce a capacitive coupling between the source/drain regions and the gate (Chan, [0003] as well as “serve an additional purpose of masking the source/drain regions from the etching.” (Chan, [0004])
Regarding claim 12, Kang discloses the semiconductor device of claim 11, wherein the gate electrode (GE) comprises an inner electrode (p0-p4), which is between adjacent ones of the semiconductor patterns (SP1-SP3), and an outer electrode (GE), which is on an uppermost one of the semiconductor patterns (SP1-SP3) relative to an upper surface of the substrate (100) being a base reference surface. (Fig. 5E)
Regarding claim 13, Kang discloses the semiconductor device of claim 11, further comprising a gate insulating layer (GI) between the semiconductor patterns (SP1-SP3) and the gate electrode (GE),
wherein the gate insulating layer (GI) is interposed between the second side surface (left) and the gate cutting pattern (CT1). (Fig. 5E)
Regarding claim 14, Kang discloses the semiconductor device of claim 11, wherein the gate cutting pattern (CT1) is in direct contact with the second side surface (left). (Fig. 9)
Regarding claim 15, Chan discloses the semiconductor device of claim 11, further comprising a bottom insulating pattern (48 in Fig. 5A) interposed between the gate electrode (30) and the active pattern (10),
wherein the bottom insulating pattern (48 in Fig. 5A) extends from the partition wall (46) to the gate cutting pattern (27). (Fig. 1a-1b and 5a-5b)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kang and Chan for similar reasons mentioned beforehand.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 20220328496 A1) in view of Chan et al. (US 20220093734 A1) as applied to acclaim 1 above, and further in view of Tsai et al. (US 20240145555 A1).
Regarding claim 7, Kang in view of Chan disclose the semiconductor device of claim 1. Kang in view of Chan do not disclose further comprising:
an interlayer insulating layer on the dam structure; and
an intermediate insulating pattern between the dam structure and the interlayer insulating layer.
However, Tsai discloses:
an interlayer insulating layer (260) on the dam structure (114); and
an intermediate insulating pattern (216) between the dam structure (114) and the interlayer insulating layer (260). (Fig. 19-20)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kang, Chan and Tsai for an interlayer insulating layer on the dam structure; and an intermediate insulating pattern between the dam structure and the interlayer insulating layer in order “meet design needs” (Tsai, [0010])
Regarding claim 8, Kang discloses the semiconductor device of claim 1, further comprising at least one active contact (AC) connected to the first and second source/drain patterns (SD1/SD2),
Kang does not disclose:
wherein a bottom surface of the active contact is between a top surface of the dam structure and an upper surface of the substrate.
However, Tsai discloses:
wherein a bottom surface of the active contact (286) is between a top surface of the dam structure (220) and an upper surface of the substrate (202). (Fig. 19-20)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kang and Tsai for similar reasons mentioned beforehand.
Regarding claim 9, Kang in view of Chan disclose the semiconductor device of claim 1. Kang in view of Chan do not disclose wherein a top surface of the dam structure is between a top surface of each of the first and second source/drain patterns and an upper surface of the substrate.
However, Tsai, discloses:
wherein a top surface of the dam structure (218) is between a top surface of each of the first and second source/drain patterns (256/257) and an upper surface of the substrate (202). (Fig. 19-20)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kang, Chan and Tsai for similar reasons mentioned beforehand.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 20220328496 A1) in view of Chan et al. (US 20220093734 A1) as applied to acclaim 1 above, and further in view of Kim (US 20220020880 A1).
Regarding claim 10, Kang in view of Chan disclose the semiconductor device of claim 1. Kang in view of Chan do not disclose further comprising a bottom insulating pattern interposed between each of the first and second source/drain patterns and the active pattern, wherein the bottom insulating pattern extends from the partition wall to the dam structure.
However, Kim discloses:
a bottom insulating pattern (IP) interposed between each of the first and second source/drain patterns (SD1/SD2) and the active pattern (SP1),
wherein the bottom insulating pattern (IP) extends from the partition wall (annotated below) to the dam structure (annotated below). (Fig. 4)
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546
546
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It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kang, Chan and Kim to have a bottom insulating pattern interposed between each of the first and second source/drain patterns and the active pattern, wherein the bottom insulating pattern extends from the partition wall to the dam structure in order to “electrically insulate the first semiconductor pattern SP1 from the second semiconductor pattern SP2.” (Kim, [0040]) so as to “educing capacitance and RC delay, thus improving the performance of the device.” (Kim, [0087])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhang et al. (US 20200350215 A1) discloses a dielectric layer (115) below the source/drains(195) but does not disclose all the features as required by the claim.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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