DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/11/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION. - The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 14 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 line 3 recited “the plurality of raised insulating pads” without mentioning “a plurality of raised insulating pads” earlier in the claim or in the independent claim it depends on. There is insufficient antecedent basis for these limitations in the claim. Claim 1 upon which claim 5 depends, does not recite “a plurality of raised insulating pads”. Therefore, it is unclear and the scope of the claim is unclear. For examination purposes, this will be interpreted as “a plurality of raised insulating pads”.
Claim 14 line 4 recited “the plurality of raised insulating pads” without mentioning “a plurality of raised insulating pads” earlier in the claim or in the independent claim it depends on. There is insufficient antecedent basis for these limitations in the claim. Claim 11 upon which claim 14 depends, does not recite “a plurality of raised insulating pads”. Therefore, it is unclear and the scope of the claim is unclear. For examination purposes, this will be interpreted as “a plurality of raised insulating pads”.
Claim 19 line 4 recited “the plurality of raised insulating pads” without mentioning “a plurality of raised insulating pads” earlier in the claim or in the independent claim it depends on. There is insufficient antecedent basis for these limitations in the claim. Claim 1 upon which claim 5 depends, does not recite “a plurality of raised insulating pads”. Therefore, it is unclear and the scope of the claim is unclear. For examination purposes, this will be interpreted as “a plurality of raised insulating pads”.
Appropriate corrections are required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 11-12, 14, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over BAEK et al. (US 20200105783 A1) in view of OGAWA et al. (US 20240107758 A1).
Regarding Independent Claim 1, BAEK et al. Figs. 1-30 discloses a vertical non-volatile memory device (“vertical memory device” ¶ [0088]), comprising:
a memory cell region (“first region A may be a cell array region for forming a memory cell array” ¶ [0033]; “cell structure 50” ¶ [0044]) including a plurality of gate lines overlapping each other in a vertical direction (“a plurality of gate electrodes 180a spaced apart from each other in the first direction” ¶ [0044]), and an insulating layer insulating the plurality of gate lines from each other in the vertical direction (“first insulation patterns 120a formed between the gate electrodes 180a. That is, the gate electrodes 180a and the first insulation patterns 120a may be repeatedly and alternately formed in the first direction” ¶ [0044]);
an extension region (“the second region B may be a pad region for forming pads of gate electrodes” ¶ [0033]) on one side of the memory cell region, the extension region including a plurality of stepped connection portions (“An edge portion in the second direction of the merged pattern structure 52 may have a step shape.” ¶ []; “The pad pattern 180c may be formed only at a step portion corresponding to an exposed edge” ¶ [0059]) having a plurality of raised pads (“a pad pattern 180c” ¶ [0057]) integrally connected to each of the plurality of gate lines (“The pad pattern 180c may be an actual pad region connecting to the gate electrode 180a” ¶ [0060]);
a peripheral circuit structure (“The third region C may be a peripheral region for forming peripheral circuits.” ¶ [0033]) in a lower portion of the memory cell region and the extension region (“the vertical memory device may have a cell over peri (COP) structure. That is, the peripheral circuits for operating the memory cells may be formed on the substrate 100 under the memory cells. As the first and second regions A and B may be positioned over the third region C, the third region C may be vertically overlapped with the first and second regions A and B.” ¶ [0034]), the peripheral circuit structure including a peripheral circuit wiring layer (“lower wirings 108” ¶ [0035]);
a through type cell contact pattern (202 in the left side of 204 in Fig. 30) in the extension region penetrating the plurality of gate lines, the insulating layer, and the plurality of stepped connection portions (“the cell contact plug 202 may extend through the second insulating interlayer 146, the first insulating interlayer 130 and the pad pattern 180c in the second region” ¶ [0073]);
a through type cell contact monitoring pattern (202 in the right side of 204 in Fig. 30) in the extension region spaced from the through type cell contact pattern (202 in the left side of 204 in Fig. 30),
However, BAEK et al. does not discloses, the through type cell contact monitoring pattern monitoring the through type cell contact pattern.
In the similar field of endeavor of memory devices, OGAWA et al. Figs. 19-21 discloses, a through type cell contact monitoring pattern (“monitor via cavity fill structures 183.” ¶ [0149]) in the extension region spaced from the through type cell contact pattern (“contact via fill structures 83” ¶ [0149]), the through type cell contact monitoring pattern monitoring the through type cell contact pattern (“provide in-situ monitoring of horizontal cross-sectional shapes of memory openings 49 or memory opening fill structures 58 without destructive analysis of devices.” ¶ [0161]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the monitoring vias of OGAWA et al. in order to provide in-situ monitoring of horizontal cross-sectional shapes of memory openings or memory opening fill structures without destructive analysis of devices. Thus, the embodiments of the present disclosure provide fast and cost-efficient monitoring of the shapes of the memory openings and/or the memory opening fill structures during manufacture of a three-dimensional memory device (OGAWA et al., ¶ [0161]).
Regarding Claim 2, BAEK et al. as modified by OGAWA et al. the limitations of claim 1. BAEK et al. further discloses, wherein:
the through type cell contact pattern is electrically connected to the plurality of raised pads in a horizontal direction (“cell contact plug 202 may be electrically connected to the pad pattern 180c,” ¶ [0154]),
However, BAEK et al. does not discloses, the through type cell contact monitoring pattern is configured to detect a defect of a horizontal connection between the plurality of raised pads and the through type cell contact pattern.
In the similar field of endeavor of memory devices, OGAWA et al. Figs. 19-21 discloses, the through type cell contact monitoring pattern (“monitor via cavity fill structures 183.” ¶ [0149]) is configured to detect a defect of a horizontal connection between the plurality of raised pads and the through type cell contact pattern (“provide in-situ monitoring of horizontal cross-sectional shapes of memory openings 49 or memory opening fill structures 58 without destructive analysis of devices.” ¶ [0161]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the monitoring vias of OGAWA et al. in order to provide in-situ monitoring of horizontal cross-sectional shapes of memory openings or memory opening fill structures without destructive analysis of devices. Thus, the embodiments of the present disclosure provide fast and cost-efficient monitoring of the shapes of the memory openings and/or the memory opening fill structures during manufacture of a three-dimensional memory device (OGAWA et al., ¶ [0161]).
Regarding Claim 4, BAEK et al. as modified by OGAWA et al. the limitations of claim 1. BAEK et al. further discloses, wherein:
the through type cell contact monitoring pattern (202 in the right side of 204 in Fig. 30) penetrates the plurality of gate lines, the insulating layer, and the plurality of stepped connection portions (“the cell contact plug 202 may extend through the second insulating interlayer 146, the first insulating interlayer 130 and the pad pattern 180c in the second region” ¶ [0073]),
the through type cell contact monitoring pattern is electrically connected to the plurality of raised pads in a horizontal direction (“the cell contact plug 202 may extend through an insulating material disposed on and under the pad pattern 180c, and may be electrically connected to the pad pattern 180c” ¶ [0075]),
However, BAEK et al. does not disclose, the through type cell contact monitoring pattern is electrically floating with respect to the peripheral circuit wiring layer in the vertical direction.
In the similar field of endeavor of memory devices, OGAWA et al. Figs. 4 and 19-21 discloses, the through type cell contact monitoring pattern is electrically floating with respect to the peripheral circuit wiring layer in the vertical direction (“monitor region 400 is provided within the kerf region KR. As will be described below, monitor structures are formed in the at least one monitor region 400 so that the shapes of memory openings that are subsequently formed in the memory array regions 100 can be indirectly monitored with an in-line measurement apparatus using the shapes of monitor openings in the at least one monitor region 400.” ¶ [0080]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the monitoring vias of OGAWA et al. in order to provide in-situ monitoring of horizontal cross-sectional shapes of memory openings or memory opening fill structures without destructive analysis of devices. Thus, the embodiments of the present disclosure provide fast and cost-efficient monitoring of the shapes of the memory openings and/or the memory opening fill structures during manufacture of a three-dimensional memory device (OGAWA et al., ¶ [0161]).
Regarding Independent Claim 11, BAEK et al. Figs. 1-30 discloses vertical non-volatile memory device (“vertical memory device” ¶ [0088]), comprising:
a peripheral circuit structure (“The third region C may be a peripheral region for forming peripheral circuits.” ¶ [0033]) including a peripheral circuit wiring layer (“the vertical memory device may have a cell over peri (COP) structure. That is, the peripheral circuits for operating the memory cells may be formed on the substrate 100 under the memory cells. As the first and second regions A and B may be positioned over the third region C, the third region C may be vertically overlapped with the first and second regions A and B.” ¶ [0034]; “lower wirings 108” ¶ [0035]);
a cell array structure (“first region A may be a cell array region for forming a memory cell array” ¶ [0033]) on the peripheral circuit structure, the cell array structure including a memory cell region (“cell structure 50” ¶ [0044]) and an extension region (“the second region B may be a pad region for forming pads of gate electrodes” ¶ [0033]),
wherein the memory cell region includes a plurality of gate lines overlapping each other in a vertical direction (“a plurality of gate electrodes 180a spaced apart from each other in the first direction” ¶ [0044]), and an insulating layer insulating the plurality of gate lines from each other in the vertical direction (“first insulation patterns 120a formed between the gate electrodes 180a. That is, the gate electrodes 180a and the first insulation patterns 120a may be repeatedly and alternately formed in the first direction” ¶ [0044]),
the extension region being on one side of the memory cell region, the extension region including a plurality of stepped connection portions (“An edge portion in the second direction of the merged pattern structure 52 may have a step shape.” ¶ [0053]]; “The pad pattern 180c may be formed only at a step portion corresponding to an exposed edge” ¶ [0059]) having a plurality of raised pads (“a pad pattern 180c” ¶ [0057]) integrally connected to each of the plurality of gate lines (“The pad pattern 180c may be an actual pad region connecting to the gate electrode 180a” ¶ [0060]);
a through type cell contact pattern in the extension region, the through type cell contact pattern penetrating the plurality of gate lines, the insulating layer, and the plurality of stepped connection portions (“the cell contact plug 202 may extend through the second insulating interlayer 146, the first insulating interlayer 130 and the pad pattern 180c in the second region” ¶ [0073]); and
However, BAEK et al. does not discloses, a through type cell contact monitoring pattern in the extension region spaced from the through type cell contact pattern, the through type cell contact monitoring pattern monitoring the through type cell contact pattern.
In the similar field of endeavor of memory devices, OGAWA et al. Figs. 19-21 discloses, a through type cell contact monitoring pattern (“monitor via cavity fill structures 183.” ¶ [0149]) in the extension region spaced from the through type cell contact pattern (“contact via fill structures 83” ¶ [0149]), the through type cell contact monitoring pattern monitoring the through type cell contact pattern (“provide in-situ monitoring of horizontal cross-sectional shapes of memory openings 49 or memory opening fill structures 58 without destructive analysis of devices.” ¶ [0161]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the monitoring vias of OGAWA et al. in order to provide in-situ monitoring of horizontal cross-sectional shapes of memory openings or memory opening fill structures without destructive analysis of devices. Thus, the embodiments of the present disclosure provide fast and cost-efficient monitoring of the shapes of the memory openings and/or the memory opening fill structures during manufacture of a three-dimensional memory device (OGAWA et al., ¶ [0161]).
Regarding Claim 12, BAEK et al. as modified by OGAWA et al. the limitations of claim 11. BAEK et al. Figs. 1-30 further discloses, wherein:
the through type cell contact monitoring pattern penetrates the plurality of gate lines, the insulating layer, and the plurality of stepped connection portions (Figs. 2-29 shows the through type cell contact monitoring pattern penetrates the plurality of gate lines, the insulating layer, and the plurality of stepped connection portions),
the through type cell contact monitoring pattern is electrically connected to the plurality of raised pads in a horizontal direction (“the cell contact plug 202 may extend through an insulating material disposed on and under the pad pattern 180c, and may be electrically connected to the pad pattern 180c” ¶ [0075]), and
However, BAEK et al. does not disclose, the through type cell contact monitoring pattern is electrically floating with respect to the peripheral circuit wiring layer in the vertical direction.
In the similar field of endeavor of memory devices, OGAWA et al. Figs. 4 and 19-21 discloses, the through type cell contact monitoring pattern is electrically floating with respect to the peripheral circuit wiring layer in the vertical direction (“monitor region 400 is provided within the kerf region KR. As will be described below, monitor structures are formed in the at least one monitor region 400 so that the shapes of memory openings that are subsequently formed in the memory array regions 100 can be indirectly monitored with an in-line measurement apparatus using the shapes of monitor openings in the at least one monitor region 400.” ¶ [0080]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the monitoring vias of OGAWA et al. in order to provide in-situ monitoring of horizontal cross-sectional shapes of memory openings or memory opening fill structures without destructive analysis of devices. Thus, the embodiments of the present disclosure provide fast and cost-efficient monitoring of the shapes of the memory openings and/or the memory opening fill structures during manufacture of a three-dimensional memory device (OGAWA et al., ¶ [0161]).
Regarding Claim 14, BAEK et al. as modified by OGAWA et al. the limitations of claim 11. BAEK et al. Figs. 1-30 further discloses, wherein:
the extension region further includes a second portion including the plurality of stepped connection portions having the plurality of raised insulating pads (“sacrificial layer 128 may include a silicon nitride material” ¶ [0101]) integrally connected to each of a plurality of sacrificial insulating lines (“sacrificial pattern 122a” ¶ [0132]) corresponding to the plurality of gate lines,
the through type cell contact monitoring pattern penetrates the plurality of sacrificial insulating lines, the insulating layer, and the plurality of stepped connection portions (Fig. 29 shows the through type cell contact monitoring pattern penetrates the plurality of sacrificial insulating lines, the insulating layer, and the plurality of stepped connection portions),
the through type cell contact monitoring pattern is electrically floating with respect to the raised insulating pad in the horizontal direction (Fig. 30 shows the through type cell contact monitoring pattern 202 is electrically floating with respect to the raised insulating pad 128 in a horizontal direction), and
the through type cell contact monitoring pattern is electrically connected to the peripheral circuit wiring layer 108 in the vertical direction (Figs. 29-30 show the through type cell contact monitoring pattern (202 in the right side of 204 in Fig. 30) is electrically connected to the peripheral circuit wiring layer 108 in the vertical direction).
Regarding Claim 17, BAEK et al. Figs. 1-30 discloses vertical non-volatile memory device (“vertical memory device” ¶ [0088]), comprising:
a peripheral circuit structure (“The third region C may be a peripheral region for forming peripheral circuits.” ¶ [0033]) on a lower substrate (Fig. 2 shows peripheral circuit is on a lower substrate), the peripheral circuit structure including a peripheral circuit wiring layer (“the vertical memory device may have a cell over peri (COP) structure. That is, the peripheral circuits for operating the memory cells may be formed on the substrate 100 under the memory cells. As the first and second regions A and B may be positioned over the third region C, the third region C may be vertically overlapped with the first and second regions A and B.” ¶ [0034]; “lower wirings 108” ¶ [0035]);
a cell array structure (“first region A may be a cell array region for forming a memory cell array” ¶ [0033]) on the peripheral circuit structure, the cell array structure including a memory cell region (“cell structure 50” ¶ [0044]) and an extension region (“the second region B may be a pad region for forming pads of gate electrodes” ¶ [0033]) on an upper substrate (Fig. 2 shows cell structure and extension on an upper substrate),
wherein the memory cell region includes a plurality of gate lines overlapping each other in a vertical direction (“a plurality of gate electrodes 180a spaced apart from each other in the first direction” ¶ [0044]) on the upper substrate, and an insulating layer insulating the plurality of gate lines from each other in the vertical direction (“first insulation patterns 120a formed between the gate electrodes 180a. That is, the gate electrodes 180a and the first insulation patterns 120a may be repeatedly and alternately formed in the first direction” ¶ [0044]),
the extension region being on one side of the memory cell region, the extension region including a plurality of stepped connection portions (“An edge portion in the second direction of the merged pattern structure 52 may have a step shape.” ¶ [0053]]; “The pad pattern 180c may be formed only at a step portion corresponding to an exposed edge” ¶ [0059]) having a plurality of raised pads (“a pad pattern 180c” ¶ [0057]) integrally connected to each of the plurality of gate lines (“The pad pattern 180c may be an actual pad region connecting to the gate electrode 180a” ¶ [0060]);
a through type cell contact pattern in the extension region, the through type cell contact pattern penetrating the plurality of gate lines, the insulating layer, and the plurality of stepped connection portions (“the cell contact plug 202 may extend through the second insulating interlayer 146, the first insulating interlayer 130 and the pad pattern 180c in the second region” ¶ [0073]), and the upper substrate; and
However, BAEK et al. does not discloses, a through type cell contact monitoring pattern in the extension region spaced from the through type cell contact pattern, the through type cell contact monitoring pattern monitoring the through type cell contact pattern.
In the similar field of endeavor of memory devices, OGAWA et al. Figs. 19-21 discloses, a through type cell contact monitoring pattern (“monitor via cavity fill structures 183.” ¶ [0149]) in the extension region spaced from the through type cell contact pattern (“contact via fill structures 83” ¶ [0149]), the through type cell contact monitoring pattern monitoring the through type cell contact pattern (“provide in-situ monitoring of horizontal cross-sectional shapes of memory openings 49 or memory opening fill structures 58 without destructive analysis of devices.” ¶ [0161]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the monitoring vias of OGAWA et al. in order to provide in-situ monitoring of horizontal cross-sectional shapes of memory openings or memory opening fill structures without destructive analysis of devices. Thus, the embodiments of the present disclosure provide fast and cost-efficient monitoring of the shapes of the memory openings and/or the memory opening fill structures during manufacture of a three-dimensional memory device (OGAWA et al., ¶ [0161]).
Regarding Claim 18, BAEK et al. as modified by OGAWA et al. the limitations of claim 17. BAEK et al. further discloses, wherein:
the through type cell contact monitoring pattern penetrates the plurality of gate lines, the insulating layer, the plurality of stepped connection portions, and the upper substrate (Figs. 2-29 shows the through type cell contact monitoring pattern penetrates the plurality of gate lines, the insulating layer, and the plurality of stepped connection portions and the upper substrate),
the through type cell contact monitoring pattern is electrically connected to the plurality of raised pads in a horizontal direction (“the cell contact plug 202 may extend through an insulating material disposed on and under the pad pattern 180c, and may be electrically connected to the pad pattern 180c” ¶ [0075]),
However, BAEK et al. does not disclose, the through type cell contact monitoring pattern is electrically floating with respect to the peripheral circuit wiring layer in the vertical direction.
In the similar field of endeavor of memory devices, OGAWA et al. Figs. 4 and 19-21 discloses, the through type cell contact monitoring pattern is electrically floating with respect to the peripheral circuit wiring layer in the vertical direction (“monitor region 400 is provided within the kerf region KR. As will be described below, monitor structures are formed in the at least one monitor region 400 so that the shapes of memory openings that are subsequently formed in the memory array regions 100 can be indirectly monitored with an in-line measurement apparatus using the shapes of monitor openings in the at least one monitor region 400.” ¶ [0080]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the monitoring vias of OGAWA et al. in order to provide in-situ monitoring of horizontal cross-sectional shapes of memory openings or memory opening fill structures without destructive analysis of devices. Thus, the embodiments of the present disclosure provide fast and cost-efficient monitoring of the shapes of the memory openings and/or the memory opening fill structures during manufacture of a three-dimensional memory device (OGAWA et al., ¶ [0161]).
Regarding Claim 19, BAEK et al. as modified by OGAWA et al. the limitations of claim 17. BAEK et al. further discloses, wherein:
the extension region further includes a second portion including the plurality of stepped connection portions having the plurality of raised insulating pads (“sacrificial layer 128 may include a silicon nitride material” ¶ [0101]) integrally connected to each of a plurality of sacrificial insulating lines (“sacrificial pattern 122a” ¶ [0132]) corresponding to the plurality of gate lines,
the through type cell contact monitoring pattern penetrates a plurality of sacrificial insulating lines, the insulating layer, the plurality of stepped connection portions, and the upper substrate (Fig. 29 shows the through type cell contact monitoring pattern penetrates the plurality of sacrificial insulating lines, the insulating layer, and the plurality of stepped connection portions and the upper substrate),
the through type cell contact monitoring pattern is electrically floating with respect to the raised insulating pad in the horizontal direction (Fig. 30 shows the through type cell contact monitoring pattern 202 is electrically floating with respect to the raised insulating pad 128 in a horizontal direction), and
the through type cell contact monitoring pattern is electrically connected to the peripheral circuit wiring layer 108 in the vertical direction (Figs. 29-30 show the through type cell contact monitoring pattern (202 in the right side of 204 in Fig. 30) is electrically connected to the peripheral circuit wiring layer 108 in the vertical direction).
Claims 3, 13, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over BAEK et al. (US 20200105783 A1) in view of OGAWA et al. (US 20240107758 A1) further in view of KIM et al. (US 20220102334 A1).
Regarding Claim 3, BAEK et al. as modified by OGAWA et al. the limitations of claim 1. BAEK et al. further discloses, wherein:
the through type cell contact pattern is electrically connected to the plurality of raised pads (“cell contact plug 202 may be electrically connected to the pad pattern 180c,” ¶ [0154]) and the peripheral circuit wiring layer (“The second and third through holes 194 and 198 may extend in the first direction to expose an upper surface of the lower wiring 108 connecting the peripheral circuit.” ¶ [0150]; “the cell contact plug 202 may be electrically connected to the lower pad pattern 108a” ¶ [0154]),
However, BAEK et al. does not disclose, the through type cell contact pattern is electrically and physically separated from the plurality of gate lines by an insulating ring.
In the similar field of endeavor of memory devices, KIM et al. Figs. 1-15 discloses, the through type cell contact pattern is electrically and physically separated from the plurality of gate lines by an insulating ring (“contact plug 126B may be surrounded by the insulating plug 115.” ¶ [0096]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the insulating layer surrounding the contact via of KIM et al. in order to isolate the cell contact pattern from the gate lines.
Regarding Claim 13, BAEK et al. as modified by OGAWA et al. the limitations of claim 11. BAEK et al. further discloses, wherein:
the through type cell contact pattern is electrically connected to the plurality of raised pads (“cell contact plug 202 may be electrically connected to the pad pattern 180c,” ¶ [0154]) and the peripheral circuit wiring layer (“The second and third through holes 194 and 198 may extend in the first direction to expose an upper surface of the lower wiring 108 connecting the peripheral circuit.” ¶ [0150]; “the cell contact plug 202 may be electrically connected to the lower pad pattern 108a” ¶ [0154]),
However, BAEK et al. does not disclose, the through type cell contact pattern is electrically and physically separated from the plurality of gate lines by an insulating ring.
In the similar field of endeavor of memory devices, KIM et al. Figs. 1-15 discloses, the through type cell contact pattern is electrically and physically separated from the plurality of gate lines by an insulating ring (“contact plug 126B may be surrounded by the insulating plug 115.” ¶ [0096]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the insulating layer surrounding the contact via of KIM et al. in order to isolate the cell contact pattern from the gate lines.
Regarding Claim 16, BAEK et al. as modified by OGAWA et al. the limitations of claim 11. BAEK et al. Figs. 1-30 further discloses, wherein:
the extension region further includes a third portion including the plurality of stepped connection portions integrally connected to each of the plurality of gate lines (“the gate electrodes 180a may be electrically connected to the connection line 180d, the conductive line 180b, and the pad pattern 180c.” ¶ [0062]),
the through type cell contact monitoring pattern penetrates the plurality of gate lines, the insulating layer, and the plurality of stepped connection portions (Figs. 2-29 shows the through type cell contact monitoring pattern penetrates the plurality of gate lines, the insulating layer, and the plurality of stepped connection portions),
However, BAEK et al. does not disclose, the through type cell contact monitoring pattern is separated from the plurality of gate lines in the horizontal direction, and
the through type cell contact monitoring pattern is electrically floating with respect to the peripheral circuit wiring layer in the vertical direction.
In the similar field of endeavor of memory devices, KIM et al. Figs. 1-15 discloses, the through type cell contact monitoring pattern is separated from the plurality of gate lines in the horizontal direction (“contact plug 126B may be surrounded by the insulating plug 115.” ¶ [0096]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the insulating layer surrounding the contact via of KIM et al. in order to isolate the cell contact pattern from the gate lines.
However, KIM et al. does not disclose, the through type cell contact monitoring pattern is electrically floating with respect to the peripheral circuit wiring layer in the vertical direction.
In the similar field of endeavor of memory devices, OGAWA et al. Figs. 4 and 19-21 discloses, the through type cell contact monitoring pattern is electrically floating with respect to the peripheral circuit wiring layer in the vertical direction (“monitor region 400 is provided within the kerf region KR. As will be described below, monitor structures are formed in the at least one monitor region 400 so that the shapes of memory openings that are subsequently formed in the memory array regions 100 can be indirectly monitored with an in-line measurement apparatus using the shapes of monitor openings in the at least one monitor region 400.” ¶ [0080]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the monitoring vias of OGAWA et al. in order to provide in-situ monitoring of horizontal cross-sectional shapes of memory openings or memory opening fill structures without destructive analysis of devices. Thus, the embodiments of the present disclosure provide fast and cost-efficient monitoring of the shapes of the memory openings and/or the memory opening fill structures during manufacture of a three-dimensional memory device (OGAWA et al., ¶ [0161]).
Regarding Claim 20, BAEK et al. as modified by OGAWA et al. the limitations of claim 17. BAEK et al. Figs. 1-30 further discloses, wherein:
the extension region further includes a third portion including the plurality of stepped connection portions integrally connected to each of the plurality of gate lines (“the gate electrodes 180a may be electrically connected to the connection line 180d, the conductive line 180b, and the pad pattern 180c.” ¶ [0062]),
the through type cell contact monitoring pattern penetrates the plurality of gate lines, the insulating layer, and the plurality of stepped connection portions and the upper substrate (Figs. 2-29 shows the through type cell contact monitoring pattern penetrates the plurality of gate lines, the insulating layer, and the plurality of stepped connection portions and the upper substrate),
However, BAEK et al. does not disclose, the through type cell contact monitoring pattern is separated from the plurality of gate lines in the horizontal direction, and
the through type cell contact monitoring pattern is electrically floating with respect to the peripheral circuit wiring layer in the vertical direction.
In the similar field of endeavor of memory devices, KIM et al. Figs. 1-15 discloses, the through type cell contact monitoring pattern is separated from the plurality of gate lines in the horizontal direction (“contact plug 126B may be surrounded by the insulating plug 115.” ¶ [0096]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the insulating layer surrounding the contact via of KIM et al. in order to isolate the cell contact pattern from the gate lines.
However, KIM et al. does not disclose, the through type cell contact monitoring pattern is electrically floating with respect to the peripheral circuit wiring layer in the vertical direction.
In the similar field of endeavor of memory devices, OGAWA et al. Figs. 4 and 19-21 discloses, the through type cell contact monitoring pattern is electrically floating with respect to the peripheral circuit wiring layer in the vertical direction (“monitor region 400 is provided within the kerf region KR. As will be described below, monitor structures are formed in the at least one monitor region 400 so that the shapes of memory openings that are subsequently formed in the memory array regions 100 can be indirectly monitored with an in-line measurement apparatus using the shapes of monitor openings in the at least one monitor region 400.” ¶ [0080]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the monitoring vias of OGAWA et al. in order to provide in-situ monitoring of horizontal cross-sectional shapes of memory openings or memory opening fill structures without destructive analysis of devices. Thus, the embodiments of the present disclosure provide fast and cost-efficient monitoring of the shapes of the memory openings and/or the memory opening fill structures during manufacture of a three-dimensional memory device (OGAWA et al., ¶ [0161]).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over BAEK et al. (US 20200105783 A1) in view of OGAWA et al. (US 20240107758 A1) further in view of NOJIMA et al. (US 20190081053 A1).
Regarding Claim 5, BAEK et al. as modified by OGAWA et al. discloses the limitations of claim 1. BAEK et al. Figs. 1-30 further discloses, wherein:
the extension region further includes a second portion including the plurality of stepped connection portions having the plurality of raised insulating pads (“sacrificial layer 128 may include a silicon nitride material” ¶ [0101]) integrally connected to each of a plurality of sacrificial insulating lines (“sacrificial pattern 122a” ¶ [0132]) corresponding to the plurality of gate lines,
the through type cell contact pattern 202 is electrically floating with respect to the raised insulating pad 128 in a horizontal direction (Fig. 30 shows the through type cell contact pattern 202 is electrically floating with respect to the raised insulating pad 128 in a horizontal direction),
However, BAEK et al. does not disclose, the through type cell contact monitoring pattern is configured to detect a defect of a vertical connection between the through type cell contact pattern and the peripheral circuit wiring layer.
In the similar field of endeavor of memory devices, NOJIMA et al. discloses, the through type cell contact monitoring pattern is configured to detect a defect of a vertical connection between the through type cell contact pattern and the peripheral circuit wiring layer (“When the contact plug CC6 is appropriately formed, the contact plugs CC6 and CC8 should exhibit relatively high luminance. As illustrated in FIG. 11B, however, luminance of the contact plugs CC6 and CC8 is low and thus, it is possible to detect matters that a defect is present in any of contact structures.” ¶ [0075]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the defect detection of the contact via of NOJIMA et al. in order to modify a formation condition of the contact plug CC or the formation condition of end portions having a step shape of the word lines WL (NOJIMA et al., [0075]).
Regarding Claim 6, BAEK et al. as modified by OGAWA et al. and NOJIMA et al. discloses the limitations of claim 5. BAEK et al. Figs. 1-30 further discloses, wherein:
the through type cell contact monitoring pattern (202 in the right side of 204 in Fig. 30) penetrates the plurality of sacrificial insulating lines, the insulating layer, and the plurality of stepped connection portions (Figs. 29-30 show the through type cell contact monitoring pattern (202 in the right side of 204 in Fig. 30) penetrates the plurality of sacrificial insulating lines, the insulating layer, and the plurality of stepped connection portions),
the through type cell contact monitoring pattern is electrically floating with respect to the raised insulating pad in the horizontal direction (Fig. 30 shows the through type cell contact monitoring pattern 202 is electrically floating with respect to the raised insulating pad 128 in a horizontal direction), and
the through type cell contact monitoring pattern is electrically connected to the peripheral circuit wiring layer 108 in the vertical direction (Figs. 29-30 show the through type cell contact monitoring pattern (202 in the right side of 204 in Fig. 30) is electrically connected to the peripheral circuit wiring layer 108 in the vertical direction).
Claims 7-10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over BAEK et al. (US 20200105783 A1) in view of OGAWA et al. (US 20240107758 A1) further in view of NOJIMA et al. (US 20190081053 A1) further in view of KIM et al. (US 20220102334 A1).
Regarding Claim 7, BAEK et al. as modified by OGAWA et al. and NOJIMA et al. discloses the limitations of claim 5. However, BAEK et al. does not disclose, wherein the through type cell contact monitoring pattern is electrically and physically separated from the plurality of sacrificial insulating lines by an insulating ring.
In the similar field of endeavor of memory devices, KIM et al. Figs. 1-15 discloses, wherein the through type cell contact monitoring pattern is electrically and physically separated from the plurality of sacrificial insulating lines by an insulating ring (“contact plug 126B may be surrounded by the insulating plug 115.” ¶ [0096]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the insulating layer surrounding the contact via of KIM et al. in order to isolate the cell contact pattern from the gate lines.
Regarding Claim 8, BAEK et al. as modified by OGAWA et al. the limitations of claim 1. BAEK et al. further discloses, wherein:
the extension region further includes a third portion including the plurality of stepped connection portions integrally connected to each of the plurality of gate lines (“the gate electrodes 180a may be electrically connected to the connection line 180d, the conductive line 180b, and the pad pattern 180c.” ¶ [0062]),
the through type cell contact pattern is separated from the plurality of gate lines in a horizontal direction (Fig. 30 shows the through type cell contact pattern 202 is separated from the plurality of gate lines 180b in a horizontal direction), and
However, BAEK et al. does not disclose, the through type cell contact monitoring pattern is configured to detect a defect of a horizontal separation between the through type cell contact pattern and the plurality of gate lines.
In the similar field of endeavor of memory devices, NOJIMA et al. discloses, the through type cell contact monitoring pattern is configured to detect a defect of a horizontal separation between the through type cell contact pattern and the plurality of gate lines (“When the contact plug CC6 is appropriately formed, the contact plugs CC6 and CC8 should exhibit relatively high luminance. As illustrated in FIG. 11B, however, luminance of the contact plugs CC6 and CC8 is low and thus, it is possible to detect matters that a defect is present in any of contact structures.” ¶ [0075]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the defect detection of the contact via of NOJIMA et al. in order to modify a formation condition of the contact plug CC or the formation condition of end portions having a step shape of the word lines WL (NOJIMA et al., [0075]).
Regarding Claim 9, BAEK et al. as modified by OGAWA et al. the limitations of claim 8. BAEK et al. Figs. 1-30 further discloses, wherein:
the through type cell contact monitoring pattern penetrates the plurality of gate lines, the insulating layer, and the plurality of stepped connection portions (Figs. 2-29 shows the through type cell contact monitoring pattern penetrates the plurality of gate lines, the insulating layer, and the plurality of stepped connection portions),
However, BAEK et al. does not disclose, the through type cell contact monitoring pattern is separated from the plurality of gate lines in the horizontal direction, and
the through type cell contact monitoring pattern is electrically floating with respect to the peripheral circuit wiring layer in the vertical direction.
In the similar field of endeavor of memory devices, KIM et al. Figs. 1-15 discloses, the through type cell contact monitoring pattern is separated from the plurality of gate lines in the horizontal direction (“contact plug 126B may be surrounded by the insulating plug 115.” ¶ [0096]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the insulating layer surrounding the contact via of KIM et al. in order to isolate the cell contact pattern from the gate lines.
However, KIM et al. does not disclose, the through type cell contact monitoring pattern is electrically floating with respect to the peripheral circuit wiring layer in the vertical direction.
In the similar field of endeavor of memory devices, OGAWA et al. Figs. 4 and 19-21 discloses, the through type cell contact monitoring pattern is electrically floating with respect to the peripheral circuit wiring layer in the vertical direction (“monitor region 400 is provided within the kerf region KR. As will be described below, monitor structures are formed in the at least one monitor region 400 so that the shapes of memory openings that are subsequently formed in the memory array regions 100 can be indirectly monitored with an in-line measurement apparatus using the shapes of monitor openings in the at least one monitor region 400.” ¶ [0080]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the monitoring vias of OGAWA et al. in order to provide in-situ monitoring of horizontal cross-sectional shapes of memory openings or memory opening fill structures without destructive analysis of devices. Thus, the embodiments of the present disclosure provide fast and cost-efficient monitoring of the shapes of the memory openings and/or the memory opening fill structures during manufacture of a three-dimensional memory device (OGAWA et al., ¶ [0161]).
Regarding Claim 10, BAEK et al. as modified by OGAWA et al. and NOJIMA et al. discloses the limitations of claim 8. However, BAEK et al. does not disclose, wherein: the through type cell contact monitoring pattern is electrically and physically separated from plurality of gate lines by an insulating ring.
In the similar field of endeavor of memory devices, KIM et al. Figs. 1-15 discloses, the through type cell contact monitoring pattern is electrically and physically separated from the plurality of gate lines by an insulating ring (“contact plug 126B may be surrounded by the insulating plug 115.” ¶ [0096]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the insulating layer surrounding the contact via of KIM et al. in order to isolate the cell contact pattern from the gate lines.
Regarding Claim 15, BAEK et al. as modified by OGAWA et al. and NOJIMA et al. discloses the limitations of claim 14. However, BAEK et al. does not disclose, wherein the through type cell contact monitoring pattern is electrically and physically separated from the plurality of sacrificial insulating lines by an insulating ring.
In the similar field of endeavor of memory devices, KIM et al. Figs. 1-15 discloses, wherein the through type cell contact monitoring pattern is electrically and physically separated from the plurality of sacrificial insulating lines by an insulating ring (“contact plug 126B may be surrounded by the insulating plug 115.” ¶ [0096]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the memory device of BAEK et al. including the insulating layer surrounding the contact via of KIM et al. in order to isolate the cell contact pattern from the gate lines.
Conclusion
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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