Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 9, 11-12 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsai (US 20230215855).
Regarding claim 1. Fig 1 of Tsai discloses A semiconductor device (16/18 regions) comprising:
a first wiring level layer (in the 42) including a lower wiring layer 44/48 (the lower 48 in the lower 46);
a second wiring level layer (in the upper 46) on the first wiring level layer and including an upper wiring layer 44/48 (the upper 48 in the lower 46, and the 48 in the upper 46);
a via level layer (in the lower 46) positioned between the first wiring level layer and the second wiring level layer and including a via 44 connecting the lower wiring layer to the upper wiring layer (Fig 1); and
a reinforcing insulating layer 46 ([0015]: the lower 46) positioned between the lower wiring layer and the upper wiring layer in the via level layer (Fig 1).
Regarding claim 2. Tsai discloses The semiconductor device of claim 1, wherein the first wiring level layer is on a semiconductor substrate 12 [0011], and the semiconductor substrate comprises:
a low voltage region 18 ([0004]/[0011]: medium voltage, MV; Note that high voltage and low voltage are relative terms. Furthermore, the applicant did not specifically claim a range for how each high and low voltage regions differ. Therefore, if one voltage is relatively lower than the other, the larger voltage is considered high voltage, and the smaller voltage is considered low voltage. Therefore, the Tsai's MV is considered LV region) including a low voltage integrated circuit [0012]; and
a high voltage region 16 ([0004]/[0011]: high-voltage, HV) including a high voltage integrated circuit [0012].
Regarding claim 3. Tsai discloses The semiconductor device of claim 2, wherein the reinforcing insulating layer is positioned in an upper portion of the high voltage region (Fig 1).
Regarding claim 5. Tsai discloses The semiconductor device of claim 1, wherein the first wiring level layer is on a semiconductor substrate 12 (Fig 1, [0011]) and the lower wiring layer extends in a Y direction (Fig 1: refer to 44 which extends in vertical direction) on the semiconductor substrate, and the upper wiring layer extends in an X direction (refer to 48 which extends in an horizontal direction) perpendicular to the Y direction on the semiconductor substrate (Fig 1: vertical vs horizontal).
Regarding claim 6. Tsai discloses Tsai discloses The semiconductor device of claim 1, wherein a distance between the lower wiring layer and the upper wiring layer is a height of the via (Fig 1).
Regarding claim 7. Tsai discloses The semiconductor device of claim 1, wherein an upper surface of the reinforcing insulating layer has a height greater than or equal to a height of an upper surface of the via (Fig 1: an upper surface of the reinforcing insulating layer has a height greater than a height of an upper surface of the via because of the upper and lower 48).
Regarding claim 9. Tsai discloses The semiconductor device of claim 1, wherein the reinforcing insulating layer is positioned between the lower wiring layer (Fig 1) and the upper wiring layer and encloses a portion of the upper wiring layer (the lower 46 encloses the lower 48 of the upper wiring layer).
Regarding claim 11. Fig 1 of Tsai discloses A semiconductor device comprising:
a semiconductor substrate 12 [0011] including a first voltage region 18 ([0004]/[0011]: MV region) and a second voltage region 16 ([0004]/[0011]: HV region);
a first wiring level layer (in the 42) on the semiconductor substrate and including a first lower wiring layer 44/48 (the lower 48 in the lower 46 of 18 region) positioned in the first voltage region and a second lower wiring layer 44/48 (the lower 48 in the lower 46 of the 16 region) positioned in the second voltage region;
a second wiring level layer (in the upper 46) on the first wiring level layer and including a first upper wiring layer 44/48 (the upper 48 in the lower 46 of 18 region, and the 48 in the upper 46 of 18 region) positioned in an upper portion (upper portion of 18) of the first voltage region and a second upper wiring layer 44/48 (the upper 48 in the lower 46 of 16 region, and the 48 in the upper 46 of 16 region) positioned in an upper portion (upper portion of 16) of the second voltage region;
a via level layer (in the lower 46) positioned between the first wiring level layer and the second wiring level layer and including a via 44 connecting the first lower wiring layer to the first upper wiring layer; and
a reinforcing insulating layer 46 ([0015]: the lower 46) positioned between the second lower wiring layer and the second upper wiring layer in the via level layer (Fig 1).
Regarding claim 12. Tsai discloses The semiconductor device of claim 11, wherein a height of the reinforcing insulating layer is greater than or equal to a height of the via (Fig 1: an upper surface of the reinforcing insulating layer has a height greater than a height of an upper surface of the via because of the upper and lower 48).
Regarding claim 15. Tsai discloses The semiconductor device of claim 11, wherein the reinforcing insulating layer is positioned between the second lower wiring layer and the second upper wiring layer (Fig 1) and encloses a portion of the second upper wiring layer (the lower 46 encloses the lower 48 of the second wiring layer).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20230215855).
Regarding claim 4. Tsai discloses The semiconductor device of claim 2, wherein the lower wiring layer includes a plurality of lower wiring layers 44 (in 42), and
the upper wiring layer includes a plurality of upper wiring layers 44/48 (in upper 46).
But Tsai does not explicitly disclose wherein a first height of the upper wiring layer in the low voltage region is greater than or equal to a second height of the upper wiring layer in the high voltage region.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the height dimension of each wiring layer is critical design choice and a key part of the technology node definition, which means the layers can be equal or, more commonly, different from each other because in modern CMOS IC design, the metal stack (interconnects) is not uniform; it is highly optimized based on the needs of the signal or power routing within that layer.
Therefore, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose the particular claimed variation because the applicant has not disclosed that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie. The claim(s) is(are) obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art. See In re Aller, 105 USPQ 233 (CCPA 1955) and In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996).
Regarding claim 13. Tsai discloses The semiconductor device of claim 11, wherein the first upper wiring layer is a low voltage wiring layer ([0004]/[0011]: because 18 is MV region MV; Note that high voltage and low voltage are relative terms. Furthermore, the applicant did not specifically claim a range for how each high and low voltage regions differ. Therefore, if one voltage is relatively lower than the other, the larger voltage is considered high voltage, and the smaller voltage is considered low voltage. Therefore, the Tsai's MV is considered LV region), and the second upper wiring layer is a high voltage wiring layer ([0004]/[0011]: because 16 is HV region).
But Tsai does not explicitly disclose wherein a height of the first upper wiring layer is greater than or equal to a height of the second upper wiring layer.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the height dimension of each wiring layer is critical design choice and a key part of the technology node definition, which means the layers can be equal or, more commonly, different from each other because in modern CMOS IC design, the metal stack (interconnects) is not uniform; it is highly optimized based on the needs of the signal or power routing within that layer.
Therefore, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose the particular claimed variation because the applicant has not disclosed that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie. The claim(s) is(are) obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art. See In re Aller, 105 USPQ 233 (CCPA 1955) and In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996).
Allowable Subject Matter
Claims 16-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 16. Fig 1 of Tsai discloses some of the claimed feature including A semiconductor device comprising: a semiconductor substrate 12 including a low voltage region 18 ([0004]/[0011]: MV region; Note that high voltage and low voltage are relative terms. Furthermore, the applicant did not specifically claim a range for how each high and low voltage regions differ. Therefore, if one voltage is relatively lower than the other, the larger voltage is considered high voltage, and the smaller voltage is considered low voltage. Therefore, the Tsai's MV is considered LV region)) and a high voltage region 16 ([0004]/[0011]: HV region);
a first wiring level layer (in the 42) on the semiconductor substrate and including a low voltage lower wiring layer 44/48 (the lower 48 in the lower 46 of 18 region) positioned in the low voltage region, a high voltage lower wiring layer 44/48 (the lower 48 in the lower 46 of 16 region) positioned in the high voltage region, and a first wiring insulating layer 42 insulating the low voltage lower wiring layer and the high voltage lower wiring layer;
a second wiring level layer (in the upper 46) on the first wiring level layer and including a low voltage upper wiring layer 44/48 (the upper 48 in the lower 46 of 18 region, and the 48 in the upper 46 of 18 region) positioned in the low voltage region, a high voltage upper wiring layer 44/48 (the upper 48 in the lower 46 of 16 region, and the 48 in the upper 46 of 16 region) positioned in the high voltage region, and a second wiring insulating layer (the upper 46) insulating the low voltage upper wiring layer and the high voltage upper wiring layer;
a via level layer (in the lower 46) positioned between the first wiring level layer and the second wiring level layer and including a via 44 connecting the low voltage lower wiring layer to the low voltage upper wiring layer and a via insulating layer 46 (the lower 46) between the first wiring level layer and the second wiring level layer.
However, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “a reinforcing insulating layer positioned between the high voltage lower wiring layer and the high voltage upper wiring layer in the via insulating layer of the via level layer”.
Claims 8, 10 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the via level layer includes a via insulating layer, and a dielectric constant of the reinforcing insulating layer is greater than a dielectric constant of the via insulating layer”.
Regarding claim 10. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the via level layer includes a via insulating layer, a dielectric constant of the reinforcing insulating layer is greater than a dielectric constant of the first wiring insulating layer, a dielectric constant of the second wiring insulating layer, and a dielectric constant of the via insulating layer”.
Regarding claim 14. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the via level layer includes a via insulating layer, a dielectric constant of the reinforcing insulating layer is greater than a dielectric constant of the first wiring insulating layer, a dielectric constant of the second wiring insulating layer, and a dielectric constant of the via insulating layer”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812