DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 8-10, 12-16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0067571 to Fratin et al. (hereinafter Fratin) in view of Ozawa et al. (US 2011/0140068, hereinafter Ozawa).
With respect to claim 1, Fratin discloses a semiconductor device (e.g., self-selecting memory cell array, see the annotated Figs. 1 and 5 below) (Fratin, Figs. 1, 5, ¶0001, ¶0020-¶0055), comprising:
a stack structure (110/215) (Fratin, Figs. 1, 5, ¶0022, ¶0027, ¶0030, ¶0052) that includes horizontal conductive layers (110-b) and interlayer insulating layers (215-b) that are alternately stacked with each other in a first direction (e.g., a vertical Z-direction);
vertical conductive layers (e.g., conductive pillar 120-b serving as bit lines (BL)) (Fratin, Figs. 1, 5, ¶0027, ¶0053) that pass through the stack structure (110/215) and extend in the first direction (e.g., the Z-direction), wherein the vertical conductive layers (120-b) have a pillar shape;
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selector layers (e.g., 505) (Fratin, Figs. 1, 5, ¶0030, ¶0053) that surround external surfaces of the vertical conductive layers (120-b), wherein the selector layers (505) include a chalcogenide material.
Further, Fratin does not specifically disclose first isolation layers that divide the horizontal conductive layers from each other and passthrough the stack structure between vertical conductive layers that are adjacent to each other in a second direction that is perpendicular to the first direction, wherein ends of the first isolation layers in the second direction are in contact with external surfaces of the selector layers.
However, Ozawa teaches forming a resistance-change memory cell array (see the annotated Figs. 1A and 10B below) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0002, ¶0032, ¶0034-¶0037, ¶0053-¶0059) in a cross-point structure, and comprising the phase change layers (13, phase change materials include chalcogenide) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0037, ¶0059) surrounding the vertical electrodes (12) passing through the horizontal conductive layers (e.g., multi-layered structure 11/16 including horizontal electrodes 11), and first isolation layers (e.g., interelectrode insulating layers 17) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0035-¶0036, ¶0055) that divide the horizontal conductive layers (11) from each other and passthrough the stack structure (11/16) between vertical conductive layers (12) that are adjacent to each other in a second direction (e.g., a vertical direction in top view of Fig.10B) that is perpendicular to the first direction (e.g., a vertical direction in 3D view of Figs. 1A, 8A-8B), wherein ends of the first isolation layers (17) in the second direction are in contact with external surfaces of the phase
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change layers (13) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0037, ¶0059).
In cross-point memory structure of Ozawa, the vertical electrodes (12) (Ozawa, Fig. 10B, ¶0059) are arranged alternately along the horizontal electrode layers (11) to enlarge a minimum distance width of the horizontal electrodes defined by the first insulation layers, in order to prevent an increase in resistance and the rate of occurrence of erroneous operations as the integration density of the memory array is enhanced, and thus to realize a memory structure suitable for high integration and with enhanced reliability.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Fratin by arranging the vertical conductive layers to enlarge a minimum distance width of the horizontal electrodes defined by the first isolation layers as taught by Ozawa to have the semiconductor device, comprising: first isolation layers that divide the horizontal conductive layers from each other and passthrough the stack structure between vertical conductive layers that are adjacent to each other in a second direction that is perpendicular to the first direction, wherein ends of the first isolation layers in the second direction are in contact with external surfaces of the selector layers, in order to provide high integration density of the cross-point memory array having high-speed response characteristics and high reliability (Ozawa, ¶0002, ¶0032, ¶0052, ¶0059).
Regarding claim 3, Fratin in view of Ozawa discloses the semiconductor device of claim 1. Further, Fratin discloses the semiconductor device, wherein the selector layers (505) (Fratin, Figs. 1, 5, ¶0030, ¶0053) extend on the external surfaces of the vertical conductive layers and surround the entire external surfaces of the vertical conductive layers (120-b).
Regarding claim 8, Fratin in view of Ozawa discloses the semiconductor device of claim 1. Further, Fratin discloses the semiconductor device, further comprising: barrier layers (145-b/145-c/145e) (Fratin, Figs. 1, 5, 6A-6B, 8, ¶0032, ¶0054-¶0055, ¶0060, ¶0074-¶0075) that cover at least one (e.g., external surfaces) of internal surfaces or the external surfaces of the selector layers (505).
Regarding claim 9, Fratin in view of Ozawa discloses the semiconductor device of claim. Further, Fratin discloses the semiconductor device, wherein the barrier layers (145-b/145-c) (Fratin, Figs. 1, 5, 6B, ¶0060, ¶0054-¶0055) include an oxide or a nitride.
Regarding claim 10, Fratin in view of Ozawa discloses the semiconductor device of claim. Further, Fratin discloses the semiconductor device, wherein the barrier layers (145-e1/145-e2) (Fratin, Fig. 8, ¶0075) have a first thickness on the internal surfaces of the selector layers, and have a second thickness that differs from the first thickness on the external surfaces of the selector layers.
Regarding claim 12, Fratin in view of Ozawa discloses the semiconductor device of claim 1. Further, Fratin discloses the semiconductor device, wherein the selector layers (505) include at least one (e.g., Te-Ge-Sb-S, Te-Ge-As, Ge-Sb-Se-Te) (Fratin, Figs. 1, 5, 6B, ¶0030, ¶0098) of sulfur (S), selenium (Se), tellurium (Te), or arsenic (As).
Regarding claim 13, Fratin in view of Ozawa discloses the semiconductor device of claim 1. Further, Fratin discloses the semiconductor device, wherein the horizontal conductive layers (110) and the vertical conductive layers (120) include a metal (Fratin, Figs. 1, 5, 6B, ¶0030, ¶0056).
With respect to claim 14, Fratin discloses a semiconductor device (e.g., self-selecting memory cell array, see the annotated Figs. 1 and 5 above) (Fratin, Figs. 1, 5, ¶0001, ¶0020-¶0055), comprising:
a stack structure (110/215) (Fratin, Figs. 1, 5, ¶0022, ¶0027, ¶0030, ¶0052) that includes horizontal conductive layers (110-b) and interlayer insulating layers (215-b) that are alternately stacked with each other in a first direction (e.g., a vertical Z-direction);
vertical structures (e.g., conductive pillar 120-b serving as bit lines (BL) and surrounded by the selector layers 505) (Fratin, Figs. 1, 5, ¶0027, ¶0030, ¶0053) that pass through the stack structure (110/215) and extend in the first direction (e.g., the Z-direction), wherein the vertical structures (120-b/505) include a selector layer (e.g., 505) (Fratin, Figs. 1, 5, ¶0030, ¶0053) and a vertical conductive layer (e.g., conductive pillar 120-b) that are sequentially disposed from the horizontal conductive layers (110).
Further, Fratin does not specifically disclose isolation layers that extending in a second direction that is perpendicular to the first direction, wherein the isolation layers divide the horizontal conductive layers from each other, wherein the isolation layers are spaced apart from each other with the vertical structures interposed therebetween and between the vertical structures arranged in a row in the second direction.
However, Ozawa teaches forming a resistance-change memory cell array (see the annotated Figs. 1A and 10B above) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0002, ¶0032, ¶0034-¶0037, ¶0053-¶0059) in a cross-point structure, and comprising the phase change layers (13, phase change materials include chalcogenide) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0037, ¶0059) surrounding the vertical electrodes (12) passing through the horizontal conductive layers (e.g., multi-layered structure 11/16 including horizontal electrodes 11), and isolation layers (e.g., interelectrode insulating layers 17) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0035-¶0036, ¶0055) that divide horizontal conductive layers (11) from each other and passthrough the stack structure (11/16) between vertical conductive layers (e.g., vertical electrodes 12) that are adjacent to each other in a second direction (e.g., a vertical direction in top view of Fig. 10B) that is perpendicular to the first direction (e.g., a vertical direction in 3D view of Figs. 1A, 8A-8B), wherein the isolation layers (17) are spaced apart from each other with the vertical structures (12/13) interposed therebetween and between the vertical structures (12/13) arranged in a row in the second direction. In cross-point memory structure of Ozawa, the vertical electrodes (12) (Ozawa, Fig. 10B, ¶0059) are arranged alternately along the horizontal electrode layers (11) to enlarge a minimum distance width of the horizontal electrodes defined by the insulation layers, in order to prevent an increase in resistance and the rate of occurrence of erroneous operations as the integration density of the memory array is enhanced, and thus to realize a memory structure suitable for high integration and with enhanced reliability.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Fratin by arranging the vertical conductive layers to enlarge a minimum distance width of the horizontal electrodes defined by the isolation layers as taught by Ozawa to have the semiconductor device, comprising: isolation layers that extending in a second direction that is perpendicular to the first direction, wherein the isolation layers divide the horizontal conductive layers from each other, wherein the isolation layers are spaced apart from each other with the vertical structures interposed therebetween and between the vertical structures arranged in a row in the second direction, in order to provide high integration density of the cross-point memory array having high-speed response characteristics and high reliability (Ozawa, ¶0002, ¶0032, ¶0052, ¶0059).
Regarding claim 15, Fratin in view of Ozawa discloses the semiconductor device of claim 14. Further, Fratin discloses the semiconductor device, wherein the horizontal conductive layers (110) (Fratin, Figs. 1, 5, ¶0027) form a word plane and the vertical conductive layer (120) forms a bit line.
Regarding claim 16, Fratin in view of Ozawa discloses the semiconductor device of claim 14. Further, Fratin discloses the semiconductor device, wherein the selector layer (505) (Fratin, Figs. 1, 5, ¶0021, ¶0030, ¶0053, ¶0098) operates as a selector (e.g., self-selecting memory cells), and has a changing resistance (e.g., memory material 505 is a variable resistance material).
Regarding claim 18, Fratin in view of Ozawa discloses the semiconductor device of claim 14. Further, Fratin does not specifically disclose that ends of the isolation layers in the second direction that are in contact with the vertical structures have a rounded shape along the vertical structures.
However, Ozawa teaches forming a resistance-change memory cell array (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0002, ¶0032, ¶0034-¶0037, ¶0053-¶0059) in a cross-point structure comprising the vertical electrodes (12) (Ozawa, Fig. 10B, ¶0059) between the isolation layers (17) and arranged alternately along the horizontal electrode layers (11) to enlarge a minimum distance width of the horizontal electrodes defined by the insulation layers, wherein ends of the isolation layers (17) in the second direction (e.g., the vertical direction in Fig. 10B) that are in contact with the vertical structures (12/13) have a rounded shape along the vertical structures, to realize a memory structure suitable for high integration and with enhanced reliability.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Fratin/Ozawa by arranging the vertical conductive layers to enlarge a minimum distance width of the horizontal electrodes defined by the insulation layers as taught by Ozawa to have the semiconductor device, wherein ends of the isolation layers in the second direction that are in contact with the vertical structures have a rounded shape along the vertical structures, in order to provide high integration density of the cross-point memory array having high-speed response characteristics and high reliability (Ozawa, ¶0002, ¶0032, ¶0052, ¶0059).
Claims 1, 3-4, and 12-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0190032 to Redaelli in view of Ozawa (US 2011/0140068).
With respect to claim 1, Redaelli discloses a semiconductor device (e.g., self-selecting storage device, see the annotated Fig. 2 below) (Redaelli, Figs. 1-2, ¶0001, ¶0013-¶0040), comprising:
a stack structure (202/204) (Redaelli, Fig. 2, ¶0020-¶0022, ¶0030) that includes horizontal conductive layers (202) and interlayer insulating layers (204) that are alternately stacked with each other in a first direction (e.g., a vertical direction);
vertical conductive layers (e.g., conductive extensions 216 serving as bit lines) (Redaelli, Fig. 2, ¶0030, ¶0032-¶0033) that pass through the stack structure (202/204) and extend in the first direction (e.g., the vertical direction), wherein the vertical conductive layers (216) have a pillar shape;
selector layers (e.g., 212, self-selecting storage element) (Redaelli, Fig. 2, ¶0030, ¶0032, ¶0035-¶0036) that surround external surfaces of the vertical conductive layers (216), wherein the selector layers (212) include a chalcogenide material.
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Further, Redaelli does not specifically disclose first isolation layers that divide the horizontal conductive layers from each other and passthrough the stack structure between vertical conductive layers that are adjacent to each other in a second direction that is perpendicular to the first direction, wherein ends of the first isolation layers in the second direction are in contact with external surfaces of the selector layers.
However, Ozawa teaches forming a resistance-change memory cell array (see the annotated Figs. 1A and 10B above) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0002, ¶0032, ¶0034-¶0037, ¶0053-¶0059) in a cross-point structure, and comprising the phase change layers (13, phase change materials include chalcogenide) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0037, ¶0059) surrounding the vertical electrodes (12) passing through the horizontal conductive layers (e.g., multi-layered structure 11/16 including horizontal electrodes 11), and first isolation layers (e.g., interelectrode insulating layers 17) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0035-¶0036, ¶0055) that divide the horizontal conductive layers (11) from each other and passthrough the stack structure (11/16) between vertical conductive layers (12) that are adjacent to each other in a second direction (e.g., a vertical direction in top view of Fig.10B) that is perpendicular to the first direction (e.g., a vertical direction in 3D view of Figs. 1A, 8A-8B), wherein ends of the first isolation layers (17) in the second direction are in contact with external surfaces of the phase change layers (13) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0037, ¶0059). In cross-point memory structure of Ozawa, the vertical electrodes (12) (Ozawa, Fig. 10B, ¶0059) are arranged alternately along the horizontal electrode layers (11) to enlarge a minimum distance width of the horizontal electrodes defined by the first insulation layers, in order to prevent an increase in resistance and the rate of occurrence of erroneous operations as the integration density of the memory array is enhanced, and thus to realize a memory structure suitable for high integration and with enhanced reliability.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Redaelli by arranging the vertical conductive layers to enlarge a minimum distance width of the horizontal electrodes defined by the first isolation layers as taught by Ozawa to have the semiconductor device, comprising: first isolation layers that divide the horizontal conductive layers from each other and passthrough the stack structure between vertical conductive layers that are adjacent to each other in a second direction that is perpendicular to the first direction, wherein ends of the first isolation layers in the second direction are in contact with external surfaces of the selector layers, in order to provide high integration density of the cross-point memory array having high-speed response characteristics and high reliability (Ozawa, ¶0002, ¶0032, ¶0052, ¶0059).
Regarding claim 3, Redaelli in view of Ozawa discloses the semiconductor device of claim 1. Further, Redaelli discloses the semiconductor device, wherein the selector layers (212) (Redaelli, Fig. 2, ¶0030, ¶0032, ¶0035-¶0036) extend on the external surfaces of the vertical conductive layers (216) and surround the entire external surfaces of the vertical conductive layers (216).
Regarding claim 4, Redaelli in view of Ozawa discloses the semiconductor device of claim 1. Further, Redaelli discloses the semiconductor device, wherein external surfaces of the selector layers (212) (Redaelli, Fig. 2, ¶0030, ¶0032, ¶0035-¶0036, ) are in direct contact with the horizontal conductive layers (202), and internal surfaces of the selector layers (212) are in direct contact (e.g., when the conductive cylinder layer 214 is optional, and no the conductive cylinder layer 214 formed between the selector layers 212 and the vertical conductive layers 216) (Redaelli, Fig. 2, ¶0040) with the vertical conductive layers (216).
Regarding claim 12, Redaelli in view of Ozawa discloses the semiconductor device of claim 1. Further, Redaelli discloses the semiconductor device, wherein the selector layers (212) include at least one (e.g., selenium-based chalcogenides or tellurium-based chalcogenides) (Redaelli, Fig. 2, ¶0035, ¶0036) of sulfur (S), selenium (Se), tellurium (Te), or arsenic (As).
Regarding claim 13, Redaelli in view of Ozawa discloses the semiconductor device of claim 1. Further, Redaelli discloses the semiconductor device, wherein the horizontal conductive layers (202) and the vertical conductive layers (216) include a metal (Redaelli, Fig. 2, ¶0021, ¶0033).
With respect to claim 14, Redaelli discloses a semiconductor device (e.g., self-selecting storage device, see the annotated Fig. 2 above) (Redaelli, Figs. 1-2, ¶0001, ¶0013-¶0040), comprising:
a stack structure (202/204) (Redaelli, Fig. 2, ¶0020-¶0022, ¶0030) that includes horizontal conductive layers (202) and interlayer insulating layers (204) that are alternately stacked with each other in a first direction (e.g., a vertical direction);
vertical structures (e.g., conductive pillar 216 serving as bit lines and surrounded by the selector layers 212) (Redaelli, Fig. 2, ¶0030, ¶0032-¶0033, ¶0035-¶0036) that pass through the stack structure (202/204) and extend in the first direction (e.g., the vertical direction), wherein the vertical structures (216/212) include a selector layer (e.g., 212, self-selecting storage element) and a vertical conductive layer (e.g., conductive pillar 216) that are sequentially disposed from the horizontal conductive layers (202).
Further, Redaelli does not specifically disclose isolation layers that extending in a second direction that is perpendicular to the first direction, wherein the isolation layers divide the horizontal conductive layers from each other, wherein the isolation layers are spaced apart from each other with the vertical structures interposed therebetween and between the vertical structures arranged in a row in the second direction.
However, Ozawa teaches forming a resistance-change memory cell array (see the annotated Figs. 1A and 10B above) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0002, ¶0032, ¶0034-¶0037, ¶0053-¶0059) in a cross-point structure, and comprising the phase change layers (13, phase change materials include chalcogenide) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0037, ¶0059) surrounding the vertical electrodes (12) passing through the horizontal conductive layers (e.g., multi-layered structure 11/16 including horizontal electrodes 11), and isolation layers (e.g., interelectrode insulating layers 17) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0035-¶0036, ¶0055) that divide horizontal conductive layers (11) from each other and passthrough the stack structure (11/16) between vertical conductive layers (e.g., vertical electrodes 12) that are adjacent to each other in a second direction (e.g., a vertical direction in top view of Fig. 10B) that is perpendicular to the first direction (e.g., a vertical direction in 3D view of Figs. 1A, 8A-8B), wherein the isolation layers (17) are spaced apart from each other with the vertical structures (12/13) interposed therebetween and between the vertical structures (12/13) arranged in a row in the second direction. In cross-point memory structure of Ozawa, the vertical electrodes (12) (Ozawa, Fig. 10B, ¶0059) are arranged alternately along the horizontal electrode layers (11) to enlarge a minimum distance width of the horizontal electrodes defined by the insulation layers, in order to prevent an increase in resistance and the rate of occurrence of erroneous operations as the integration density of the memory array is enhanced, and thus to realize a memory structure suitable for high integration and with enhanced reliability.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Redaelli by arranging the vertical conductive layers to enlarge a minimum distance width of the horizontal electrodes defined by the isolation layers as taught by Ozawa to have the semiconductor device, comprising: isolation layers that extending in a second direction that is perpendicular to the first direction, wherein the isolation layers divide the horizontal conductive layers from each other, wherein the isolation layers are spaced apart from each other with the vertical structures interposed therebetween and between the vertical structures arranged in a row in the second direction, in order to provide high integration density of the cross-point memory array having high-speed response characteristics and high reliability (Ozawa, ¶0002, ¶0032, ¶0052, ¶0059).
Regarding claim 15, Redaelli in view of Ozawa discloses the semiconductor device of claim 14. Further, Redaelli discloses the semiconductor device, wherein the horizontal conductive layers (202) (Redaelli, Fig. 2, ¶0021, ¶0033) form a word plane and the vertical conductive layer (216) forms a bit line.
Regarding claim 16, Redaelli in view of Ozawa discloses the semiconductor device of claim 14. Further, Redaelli discloses the semiconductor device, wherein the selector layer (212) (Redaelli, Fig. 2, ¶0035-¶0036) operates as a selector (e.g., self-selecting storage cells), and has a changing resistance (e.g., chalcogenides changing phase/resistance).
Regarding claim 17, Redaelli in view of Ozawa discloses the semiconductor device of claim 14. Further, Redaelli discloses the semiconductor device, wherein the selector layer (212) (Redaelli, Fig. 2, ¶0015, ¶0035-¶0036) is a single material layer and is in direct contact (e.g., when the conductive cylinder layer 214 is optional, and no the conductive cylinder layer 214 formed between the selector layers 212 and the vertical conductive layers 216) (Redaelli, Fig. 2, ¶0040) with the horizontal conductive layers (202) and the vertical conductive layer (216).
Regarding claim 18, Fratin in view of Ozawa discloses the semiconductor device of claim 14. Further, Fratin does not specifically disclose that ends of the isolation layers in the second direction that are in contact with the vertical structures have a rounded shape along the vertical structures.
However, Ozawa teaches forming a resistance-change memory cell array (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0002, ¶0032, ¶0034-¶0037, ¶0053-¶0059) in a cross-point structure comprising the vertical electrodes (12) (Ozawa, Fig. 10B, ¶0059) between the isolation layers (17) and arranged alternately along the horizontal electrode layers (11) to enlarge a minimum distance width of the horizontal electrodes defined by the insulation layers, wherein ends of the isolation layers (17) in the second direction (e.g., the vertical direction in Fig. 10B) that are in contact with the vertical structures (12/13) have a rounded shape along the vertical structures, to realize a memory structure suitable for high integration and with enhanced reliability.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Fratin/Ozawa by arranging the vertical conductive layers to enlarge a minimum distance width of the horizontal electrodes defined by the insulation layers as taught by Ozawa to have the semiconductor device, wherein ends of the isolation layers in the second direction that are in contact with the vertical structures have a rounded shape along the vertical structures, in order to provide high integration density of the cross-point memory array having high-speed response characteristics and high reliability (Ozawa, ¶0002, ¶0032, ¶0052, ¶0059).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0067571 to Fratin in view of Ozawa (US 2011/0140068) as applied to claim 1, and further in view of Lue (US 2022/0013535).
Regarding claim 2, Fratin in view of Ozawa discloses the semiconductor device of claim 1. Further, Fratin does not specifically disclose that in a third direction that is perpendicular to the first and second directions, each of the horizontal conductive layers includes first to fourth sub conductive layers divided from each other, and the first and third sub conductive layers are electrically connected to each other, and the second and fourth conductive layers are electrically connected to each other.
However, Ozawa teaches forming a resistance-change memory cell array (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0002, ¶0032, ¶0034-¶0037, ¶0053-¶0059) in a cross-point structure comprising the vertical electrodes (12) (Ozawa, Figs. 10B, ¶0059) between the isolation layers (17), wherein in a third direction (e.g., a horizontal direction in top view of Fig. 10B) that is perpendicular to the first (e.g., vertical direction in Fig. 1A) and second (e.g., a vertical direction in top view of Fig.10B) directions, each of the horizontal conductive layers (11) includes first to third sub conductive layers divided from each other, to realize a memory structure suitable for high integration and with enhanced reliability.
Further, Lue teaches forming a three-dimensional memory device (Lue, Figs. 1A-1I, ¶0004, ¶0035-¶0052) comprising vertical memory structures (e.g., channel pillars 110/112) (Lue, Fig. 1H, ¶0043, ¶0047) between the isolation layers (120) in a second direction (e.g., horizontal direction of Fig. 1H) and extending through the horizontal conductive layers (126) in a first direction (e.g., vertical direction of Fig. 1F), such that in a third direction (e.g., vertical direction of Fig. 1H) that is perpendicular to the first (e.g., vertical direction of Fig. 1F) and second (e.g., horizontal direction of Fig. 1H) directions, each of the horizontal conductive layers (126) includes first to fourth sub conductive layers divided from each other, and the first and third sub conductive layers are electrically connected (e.g., the first conductive wire W1 connects the memory cells of the odd rows) (Lue, Fig. 1I, ¶0052) to each other, and the second and fourth conductive layers are electrically connected to each other (e.g., the second conductive wire W2 connects the memory cells of the even rows), to provide memory cells having arc-shape channel pillars to generate the curvature effect to enhance the operation window, to provide longer channel length, and to improve deice performance.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Fratin/Ozawa by arranging the vertical conductive layers to enlarge a minimum distance width of the horizontal electrodes defined by the isolation layers as taught by Ozawa, and forming a plurality of isolation layers between the memory cells to divide the horizontal conductive layers into first to fourth sublayers (corresponding to the first to fourth rows) as taught by Lue, wherein the first and second conductive wires connect the memory cells in the odd and even rows, respectively, to have the semiconductor device, wherein in a third direction that is perpendicular to the first and second directions, each of the horizontal conductive layers includes first to fourth sub conductive layers divided from each other, and the first and third sub conductive layers are electrically connected to each other, and the second and fourth conductive layers are electrically connected to each others, in order to provide high integration density of the cross-point memory array having high-speed response characteristics and high reliability; to provide memory cells having arc-shape channel pillars to generate the curvature effect to enhance the operation window, to provide longer channel length, and to improve deice performance (Ozawa, ¶0002, ¶0032, ¶0052, ¶0059; Lue, ¶0004, ¶0050).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0190032 to Redaelli in view of Ozawa (US 2011/0140068) as applied to claim 1, and further in view of Lue (US 2022/0013535).
Regarding claim 2, Redaelli n view of Ozawa discloses the semiconductor device of claim 1. Further, Redaelli does not specifically disclose that in a third direction that is perpendicular to the first and second directions, each of the horizontal conductive layers includes first to fourth sub conductive layers divided from each other, and the first and third sub conductive layers are electrically connected to each other, and the second and fourth conductive layers are electrically connected to each other.
However, Ozawa teaches forming a resistance-change memory cell array (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0002, ¶0032, ¶0034-¶0037, ¶0053-¶0059) in a cross-point structure comprising the vertical electrodes (12) (Ozawa, Figs. 10B, ¶0059) between the isolation layers (17), wherein in a third direction (e.g., a horizontal direction in top view of Fig. 10B) that is perpendicular to the first (e.g., vertical direction in Fig. 1A) and second (e.g., a vertical direction in top view of Fig.10B) directions, each of the horizontal conductive layers (11) includes first to third sub conductive layers divided from each other, to realize a memory structure suitable for high integration and with enhanced reliability.
Further, Lue teaches forming a three-dimensional memory device (Lue, Figs. 1A-1I, ¶0004, ¶0035-¶0052) comprising vertical memory structures (e.g., channel pillars 110/112) (Lue, Fig. 1H, ¶0043, ¶0047) between the isolation layers (120) in a second direction (e.g., horizontal direction of Fig. 1H) and extending through the horizontal conductive layers (126) in a first direction (e.g., vertical direction of Fig. 1F), such that in a third direction (e.g., vertical direction of Fig. 1H) that is perpendicular to the first (e.g., vertical direction of Fig. 1F) and second (e.g., horizontal direction of Fig. 1H) directions, each of the horizontal conductive layers (126) includes first to fourth sub conductive layers divided from each other, and the first and third sub conductive layers are electrically connected (e.g., the first conductive wire W1 connects the memory cells of the odd rows) (Lue, Fig. 1I, ¶0052) to each other, and the second and fourth conductive layers are electrically connected to each other (e.g., the second conductive wire W2 connects the memory cells of the even rows), to provide memory cells having arc-shape channel pillars to generate the curvature effect to enhance the operation window, to provide longer channel length, and to improve deice performance.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Redaelli/Ozawa by arranging the vertical conductive layers to enlarge a minimum distance width of the horizontal electrodes defined by the isolation layers as taught by Ozawa, and forming a plurality of isolation layers between the memory cells to divide the horizontal conductive layers into first to fourth sublayers (corresponding to the first to fourth rows) as taught by Lue, wherein the first and second conductive wires connect the memory cells in the odd and even rows, respectively, to have the semiconductor device, wherein in a third direction that is perpendicular to the first and second directions, each of the horizontal conductive layers includes first to fourth sub conductive layers divided from each other, and the first and third sub conductive layers are electrically connected to each other, and the second and fourth conductive layers are electrically connected to each others, in order to provide high integration density of the cross-point memory array having high-speed response characteristics and high reliability; to provide memory cells having arc-shape channel pillars to generate the curvature effect to enhance the operation window, to provide longer channel length, and to improve deice performance (Ozawa, ¶0002, ¶0032, ¶0052, ¶0059; Lue, ¶0004, ¶0050).
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0067571 to Fratin in view of Ozawa (US 2011/0140068) as applied to claim 1, and further in view of Jiang et al. (US 2023/0061925, hereinafter Jiang).
Regarding claims 5-7, Fratin in view of Ozawa discloses the semiconductor device of claim 1. Further, Fratin does not specifically disclose the semiconductor device, further comprising: second isolation layers that extend in a third direction that is perpendicular to the first and second directions, wherein the second isolation layers divide the vertical conductive layers (as claimed in claim 5); wherein the second isolation layers are spaced apart from the first isolation layers (as claimed in claim 6); wherein the second isolation layers further divide the selector layers, and ends of the second isolation layers in the third direction are positioned outside of the selector layers (as claimed in claim 7).
However, Jiang teaches forming a three-dimensional (3D) memory device (Jiang, Figs. 1A, 1C-1D, ¶0013, ¶0016-¶0036) comprising vertical conductive structures (e.g., source/drain conductive lines 104/106) (Lue, Fig. 1A, 1C-1D, ¶0018-¶0019) separated with second isolation layers (112) that extend in a third direction (e.g., X-direction) that is perpendicular to the first and second directions (e.g., Z and Y directions), wherein the second isolation layers (112) divide the vertical conductive layers (104/106), wherein the second isolation layers (112) are spaced apart from the first isolation layers (114/116) that extend in the second direction (e.g., Y-direction); and wherein the second isolation layers (112) further divide the channel layers (108), and ends of the second isolation layers (112) in the third direction (X direction) are positioned outside of the channel layers (108), to provide 3D memory device having a plurality of memory cells connected at a high density in parallel to achieve a sum-of product operation (Jiang, ¶0013, ¶0016, ¶0036).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Fratin/Ozawa by forming second isolation layers extending in a third direction to separate the vertical conductive structures in a second direction as taught by Jiang to have the semiconductor device, further comprising: second isolation layers that extend in a third direction that is perpendicular to the first and second directions, wherein the second isolation layers divide the vertical conductive layers (as claimed in claim 5); wherein the second isolation layers are spaced apart from the first isolation layers (as claimed in claim 6); wherein the second isolation layers further divide the selector layers, and ends of the second isolation layers in the third direction are positioned outside of the selector layers (as claimed in claim 7), in order to provide 3D memory device having a plurality of memory cells connected at a high density in parallel to achieve a sum-of product operation (Jiang, ¶0013, ¶0016, ¶0036).
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0190032 to Redaelli in view of Ozawa (US 2011/0140068) as applied to claim 1, and further in view of Jiang (US 2023/0061925).
Regarding claims 5-7, Redaelli in view of Ozawa discloses the semiconductor device of claim 1. Further, Redaelli does not specifically disclose the semiconductor device, further comprising: second isolation layers that extend in a third direction that is perpendicular to the first and second directions, wherein the second isolation layers divide the vertical conductive layers (as claimed in claim 5); wherein the second isolation layers are spaced apart from the first isolation layers (as claimed in claim 6); wherein the second isolation layers further divide the selector layers, and ends of the second isolation layers in the third direction are positioned outside of the selector layers (as claimed in claim 7).
However, Jiang teaches forming a three-dimensional (3D) memory device (Jiang, Figs. 1A, 1C-1D, ¶0013, ¶0016-¶0036) comprising vertical conductive structures (e.g., source/drain conductive lines 104/106) (Lue, Fig. 1A, 1C-1D, ¶0018-¶0019) separated with second isolation layers (112) that extend in a third direction (e.g., X-direction) that is perpendicular to the first and second directions (e.g., Z and Y directions), wherein the second isolation layers (112) divide the vertical conductive layers (104/106), wherein the second isolation layers (112) are spaced apart from the first isolation layers (114/116) that extend in the second direction (e.g., Y-direction); and wherein the second isolation layers (112) further divide the channel layers (108), and ends of the second isolation layers (112) in the third direction (X direction) are positioned outside of the channel layers (108), to provide 3D memory device having a plurality of memory cells connected at a high density in parallel to achieve a sum-of product operation (Jiang, ¶0013, ¶0016, ¶0036).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Redaelli/Ozawa by forming second isolation layers extending in a third direction to separate the vertical conductive structures in a second direction as taught by Jiang to have the semiconductor device, further comprising: second isolation layers that extend in a third direction that is perpendicular to the first and second directions, wherein the second isolation layers divide the vertical conductive layers (as claimed in claim 5); wherein the second isolation layers are spaced apart from the first isolation layers (as claimed in claim 6); wherein the second isolation layers further divide the selector layers, and ends of the second isolation layers in the third direction are positioned outside of the selector layers (as claimed in claim 7), in order to provide 3D memory device having a plurality of memory cells connected at a high density in parallel to achieve a sum-of product operation (Jiang, ¶0013, ¶0016, ¶0036).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0067571 to Fratin in view of Ozawa (US 2011/0140068) as applied to claim 1, and further in view of Takahashi et al. (US 2020/0395408, hereinafter Takahashi).
Regarding claim 11, Fratin in view of Ozawa discloses the semiconductor device of claim 1. Further, Fratin does not specifically disclose that a thickness of each of the selector layers is in a range from about 10 nm to about 30 nm.
However, Takahashi teaches forming a three-dimensional memory device (Takahasi, ¶0118-¶0120) comprising a selector layer (56) including chalcogenide material, wherein the composition and thickness of the selector material (56) is selected such that the resistivity of the selector material (56) decreases at least two orders of magnitude upon application of a specific bias voltage (e.g., between 1 V and 6V), to provide an electrical connection or an electrical isolation depending on magnitude and/or polarity of the applied bias voltage. The thickness of the selector layer (56) ranges from 1 nm to 50 nm or from 5 nm to 25 nm. (Takahasi, ¶0120).
The claimed range overlaps the range of Takahashi. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Fratin/Ozawa by forming the selector layer having specific composition and thickness as taught by Takahashi to have the semiconductor device, wherein a thickness of each of the selector layers is in a range from about 10 nm to about 30 nm, in order to obtain a reliable selector material capable of providing an electrical connection or an electrical isolation depending on magnitude and/or polarity of the applied bias voltage (Takahashi, ¶0119-¶0120).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0190032 to Redaelli in view of Ozawa (US 2011/0140068) as applied to claim 1, and further in view of Takahashi et al. (US 2020/0395408, hereinafter Takahashi).
Regarding claim 11, Redaelli in view of Ozawa discloses the semiconductor device of claim 1. Further, Redaelli does not specifically disclose that a thickness of each of the selector layers is in a range from about 10 nm to about 30 nm.
However, Takahashi teaches forming a three-dimensional memory device (Takahasi, ¶0118-¶0120) comprising a selector layer (56) including chalcogenide material, wherein the composition and thickness of the selector material (56) is selected such that the resistivity of the selector material (56) decreases at least two orders of magnitude upon application of a specific bias voltage (e.g., between 1 V and 6V), to provide an electrical connection or an electrical isolation depending on magnitude and/or polarity of the applied bias voltage. The thickness of the selector layer (56) ranges from 1 nm to 50 nm or from 5 nm to 25 nm. (Takahasi, ¶0120).
The claimed range overlaps the range of Takahashi. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Redaelli/Ozawa by forming the selector layer having specific composition and thickness as taught by Takahashi to have the semiconductor device, wherein a thickness of each of the selector layers is in a range from about 10 nm to about 30 nm, in order to obtain a reliable selector material capable of providing an electrical connection or an electrical isolation depending on magnitude and/or polarity of the applied bias voltage (Takahashi, ¶0119-¶0120).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0067571 to Fratin in view of Ozawa (US 2011/0140068) and Lue (US 2022/0013535).
With respect to claim 19, Fratin discloses a semiconductor device (e.g., self-selecting memory cell array, see the annotated Figs. 1 and 5 above) (Fratin, Figs. 1, 5, ¶0001, ¶0020-¶0055), comprising:
a stack structure (110/215) (Fratin, Figs. 1, 5, ¶0022, ¶0027, ¶0030, ¶0052) that includes horizontal conductive layers (110-b) and interlayer insulating layers (215-b) that are alternately stacked with each other in a first direction (e.g., a vertical Z-direction);
vertical structures (e.g., conductive pillar 120-b serving as bit lines (BL) and surrounded by the selector layers 505) (Fratin, Figs. 1, 5, ¶0027, ¶0030, ¶0053) that pass through the stack structure (110/215) and extend in the first direction (e.g., the Z-direction), wherein the vertical structures (120-b/505) include a selector layer (e.g., 505) (Fratin, Figs. 1, 5, ¶0030, ¶0053) and a vertical conductive layer (e.g., conductive pillar 120-b) that are sequentially disposed from the horizontal conductive layers (110).
Further, Fratin does not specifically disclose isolation layers that extend in a second direction that is perpendicular to the first direction, wherein the isolation layers extend between adjacent vertical structures and divide the horizontal conductive layers into sequentially disposed first to fourth sub conductive layers, wherein the first and third sub conductive layers are electrically connected to each other, and the second and fourth conductive layers are electrically connected to each other.
However, Ozawa teaches forming a resistance-change memory cell array (see the annotated Figs. 1A and 10B above) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0002, ¶0032, ¶0034-¶0037, ¶0053-¶0059) in a cross-point structure, and comprising the phase change layers (13, phase change materials include chalcogenide) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0037, ¶0059) surrounding the vertical electrodes (12) passing through the horizontal conductive layers (e.g., multi-layered structure 11/16 including horizontal electrodes 11), and isolation layers (e.g., interelectrode insulating layers 17) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0035-¶0036, ¶0055) that extend between adjacent vertical structures (12) and divide the horizontal conductive layers (11) into sequentially disposed first to third sub conductive layers, arranged in a row in the second direction. In cross-point memory structure of Ozawa, the vertical electrodes (12) (Ozawa, Fig. 10B, ¶0059) are arranged alternately along the horizontal electrode layers (11) to enlarge a minimum distance width of the horizontal electrodes defined by the insulation layers, in order to prevent an increase in resistance and the rate of occurrence of erroneous operations as the integration density of the memory array is enhanced, and thus to realize a memory structure suitable for high integration and with enhanced reliability.
Further, Lue teaches forming a three-dimensional memory device (see the annotated Fig. 1H below) (Lue, Figs. 1A-1I, ¶0004, ¶0035-¶0052) comprising vertical memory structures (e.g., channel pillars 110/112) (Lue, Fig. 1H, ¶0043, ¶0047) between the isolation layers (120) in a second direction (e.g., horizontal direction of Fig. 1H) and extending through the horizontal conductive layers (126) in a first direction (e.g., vertical direction of Fig. 1F), such that in a third direction (e.g., vertical direction of Fig. 1H), each of the horizontal conductive layers (126) includes first to fourth sub conductive layers divided from each other, and the first and third sub conductive layers are electrically connected (e.g., the first conductive wire W1 connects the memory cells of the odd rows) (Lue, Fig. 1I, ¶0052) to each other, and the second and fourth conductive layers are electrically connected to each other (e.g., the second conductive wire W2 connects the memory cells of the even rows), to provide memory cells having arc-shape channel pillars to generate the curvature effect to enhance the operation window, to provide
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longer channel length, and to improve device performance.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Fratin by arranging the vertical conductive layers to enlarge a minimum distance width of the horizontal electrodes defined by the isolation layers as taught by Ozawa, and forming a plurality of isolation layers between the memory cells to divide the horizontal conductive layers into first to fourth sublayers (in the first to fourth rows) as taught by Lue, wherein the first and second conductive wires connect the memory cells in the odd and even rows, respectively, to have the semiconductor device, comprising: isolation layers that extend in a second direction that is perpendicular to the first direction, wherein the isolation layers extend between adjacent vertical structures and divide the horizontal conductive layers into sequentially disposed first to fourth sub conductive layers, wherein the first and third sub conductive layers are electrically connected to each other, and the second and fourth conductive layers are electrically connected to each other, in order to provide high integration density of the cross-point memory array having high-speed response characteristics and high reliability; to provide memory cells having arc-shape channel pillars to generate the curvature effect to enhance the operation window, to provide longer channel length, and to improve device performance (Ozawa, ¶0002, ¶0032, ¶0052, ¶0059; Lue, ¶0004, ¶0050).
Regarding claim 20, Fratin in view of Ozawa and Lue discloses the semiconductor device of claim 19. Further, Fratin does not specifically disclose that the selector layer forms two memory cells between the selector layer and the respective horizontal conductive layers.
However, Ozawa teaches forming a 2-cell portion of a resistance-change memory cell array (Ozawa, Figs. 11A-11B, 12B, ¶0060-¶0063) wherein the phase change layer (13) is divided by the insulating layer (17) such that shorting failure between the adjacent horizontal electrodes (11) is avoided to suppress leakage current and to reduce power consumption.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Fratin/Ozawa/Lue by forming a 2-cell portion as taught by Ozawa, wherein the selector layer of Fratin is divided with the isolation layer as the phase change layer of Ozawa to have the semiconductor device, wherein the selector layer forms two memory cells between the selector layer and the respective horizontal conductive layers, in order to avoid shorting failure between the adjacent horizontal electrodes to suppress leakage current and to reduce power consumption (Ozawa, ¶0062).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0190032 to Redaelli in view of Ozawa (US 2011/0140068) and Lue (US 2022/0013535).
With respect to claim 19, Redaelli discloses a semiconductor device (e.g., self-selecting storage device, see the annotated Fig. 2 above) (Redaelli, Figs. 1-2, ¶0001, ¶0013-¶0040), comprising:
a stack structure (202/204) (Redaelli, Fig. 2, ¶0020-¶0022, ¶0030) that includes horizontal conductive layers (202) and interlayer insulating layers (204) that are alternately stacked with each other in a first direction (e.g., a vertical direction);
vertical structures (e.g., conductive pillar 216 serving as bit lines and surrounded by the selector layers 212) (Redaelli, Fig. 2, ¶0030, ¶0032-¶0033, ¶0035-¶0036) that pass through the stack structure (202/204) and extend in the first direction (e.g., the vertical direction), wherein the vertical structures (216/212) include a selector layer (e.g., 212, self-selecting storage element) and a vertical conductive layer (e.g., conductive pillar 216) that are sequentially disposed from the horizontal conductive layers (202).
Further, Redaelli does not specifically disclose isolation layers that extend in a second direction that is perpendicular to the first direction, wherein the isolation layers extend between adjacent vertical structures and divide the horizontal conductive layers into sequentially disposed first to fourth sub conductive layers, wherein the first and third sub conductive layers are electrically connected to each other, and the second and fourth conductive layers are electrically connected to each other.
However, Ozawa teaches forming a resistance-change memory cell array (see the annotated Figs. 1A and 10B above) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0002, ¶0032, ¶0034-¶0037, ¶0053-¶0059) in a cross-point structure, and comprising the phase change layers (13, phase change materials include chalcogenide) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0037, ¶0059) surrounding the vertical electrodes (12) passing through the horizontal conductive layers (e.g., multi-layered structure 11/16 including horizontal electrodes 11), and isolation layers (e.g., interelectrode insulating layers 17) (Ozawa, Figs. 1A, 8A-8B, 10B, ¶0035-¶0036, ¶0055) that extend between adjacent vertical structures (12) and divide the horizontal conductive layers (11) into sequentially disposed first to third sub conductive layers, arranged in a row in the second direction. In cross-point memory structure of Ozawa, the vertical electrodes (12) (Ozawa, Fig. 10B, ¶0059) are arranged alternately along the horizontal electrode layers (11) to enlarge a minimum distance width of the horizontal electrodes defined by the insulation layers, in order to prevent an increase in resistance and the rate of occurrence of erroneous operations as the integration density of the memory array is enhanced, and thus to realize a memory structure suitable for high integration and with enhanced reliability.
Further, Lue teaches forming a three-dimensional memory device (see the annotated Fig. 1I above) (Lue, Figs. 1A-1I, ¶0004, ¶0035-¶0052) comprising vertical memory structures (e.g., channel pillars 110/112) (Lue, Fig. 1H, ¶0043, ¶0047) between the isolation layers (120) in a second direction (e.g., horizontal direction of Fig. 1H) and extending through the horizontal conductive layers (126) in a first direction (e.g., vertical direction of Fig. 1F), such that in a third direction (e.g., vertical direction of Fig. 1H), each of the horizontal conductive layers (126) includes first to fourth sub conductive layers divided from each other, and the first and third sub conductive layers are electrically connected (e.g., the first conductive wire W1 connects the memory cells of the odd rows) (Lue, Fig. 1I, ¶0052) to each other, and the second and fourth conductive layers are electrically connected to each other (e.g., the second conductive wire W2 connects the memory cells of the even rows), to provide memory cells having arc-shape channel pillars to generate the curvature effect to enhance the operation window, to provide longer channel length, and to improve deice performance.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Redaelli by arranging the vertical conductive layers to enlarge a minimum distance width of the horizontal electrodes defined by the isolation layers as taught by Ozawa, and forming a plurality of isolation layers between the memory cells to divide the horizontal conductive layers into first to fourth sublayers (in the first to fourth rows) as taught by Lue, wherein the first and second conductive wires connect the memory cells in the odd and even rows, respectively, to have the semiconductor device, comprising: isolation layers that extend in a second direction that is perpendicular to the first direction, wherein the isolation layers extend between adjacent vertical structures and divide the horizontal conductive layers into sequentially disposed first to fourth sub conductive layers, wherein the first and third sub conductive layers are electrically connected to each other, and the second and fourth conductive layers are electrically connected to each other, in order to provide high integration density of the cross-point memory array having high-speed response characteristics and high reliability; to provide memory cells having arc-shape channel pillars to generate the curvature effect to enhance the operation window, to provide longer channel length, and to improve deice performance (Ozawa, ¶0002, ¶0032, ¶0052, ¶0059; Lue, ¶0004, ¶0050).
Regarding claim 20, Redaelli in view of Ozawa and Lue discloses the semiconductor device of claim 19. Further, Redaelli does not specifically disclose that the selector layer forms two memory cells between the selector layer and the respective horizontal conductive layers.
However, Ozawa teaches forming a 2-cell portion of a resistance-change memory cell array (Ozawa, Figs. 11A-11B, 12B, ¶0060-¶0063) wherein the phase change layer (13) is divided by the insulating layer (17) such that shorting failure between the adjacent horizontal electrodes (11) is avoided to suppress leakage current and to reduce power consumption.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Redaelli/Ozawa/Lue by forming a 2-cell portion as taught by Ozawa, wherein the selector layer of Redaelli is divided with the isolation layer as the phase change layer of Ozawa to have the semiconductor device, wherein the selector layer forms two memory cells between the selector layer and the respective horizontal conductive layers, in order to avoid shorting failure between the adjacent horizontal electrodes to suppress leakage current and to reduce power consumption (Ozawa, ¶0062).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891