DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I, Species ID (Fig. 10, Claims 1-17) in the reply filed on 02/03/2026 is acknowledged. The traversal is on the ground(s) that the search and examination of all the claims may be made without serious burden. This is not found persuasive because restriction for examination purposes as indicated is proper because all these inventions listed in this action are independent or distinct and the species are independent or distinct because of the reasons given requirement for Restriction/Election from 02/03/2026 and there would be a serious search and/or examination burden if restriction were not required because at least the following reason(s) apply:
the inventions have acquired a separate status in the art in view of their different classification
the inventions have acquired a separate status in the art due to their recognized divergent subject matter
the inventions require a different field of search (e.g., searching different classes /subclasses or electronic resources, or employing different search strategies or search queries).
the prior art applicable to one invention would not likely be applicable to another invention.
Further, there is a search and/or examination burden for the patentably distinct species as set forth above because at least the following reason(s) apply:
the species require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search queries).
the prior art applicable to one species would not likely be applicable to the other species.
In addition, these species are not obvious variants of each other based on the current record.
The requirement is still deemed proper and is therefore made FINAL.
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 02/03/2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the
“the at least one first alignment pattern includes a plurality of first alignment patterns such that the plurality of first alignment patterns are disposed farther from the semiconductor chip than the first bonding pad.” of Claim 14.
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8-11 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over in Kim et al. (US 2008/0284048 A1) view of Ryan (US 2007/0134903 A1).
Regarding Claim 1, Kim (Fig. 1, 2) discloses a semiconductor package comprising:
a substrate (10, 12) including an upper pad (14b) and at least one alignment pad (14a) on an upper surface of the substrate (10, 12) such that the upper pad is adjacent to the at least one alignment pad (Fig. 1 lower left corner) (See 14a and 14b adjacent to each other);
a first bonding pad (16, 17 above 14b) on the upper pad (14b), the first bonding pad including a first trench (See 17 in aperture 15b) on an upper surface of the first bonding pad (top 17), the first trench extending in a first direction (See direction of I-I and II-II of Fig. 2D);
at least one first alignment pattern (16, 17 above 14a) on the at least one alignment pad (14a) such that the at least one first alignment pattern (16, 17 above 14a) is adjacent to the first bonding pad (16, 17 above 14b) and the at least one first alignment pattern (16, 17, 18a) is aligned with the first trench in the first direction (Direction of Fig. 2D).
Kim does not explicitly disclose a semiconductor chip on the substrate; and
a first bonding wire connecting the semiconductor chip to the first bonding pad, the first bonding wire contacting the first bonding pad and partially filling the first trench.
Ryan (Fig. 1A, 4, 5) discloses a semiconductor chip (IC); and
a first bonding wire (510) connecting the semiconductor chip (IC) to a first bonding pad (150), the first bonding wire contacting the first bonding pad (150) and partially filling a first trench (see trench in 150 in Fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor package in Kim in view of Ryan such that a semiconductor chip on the substrate; and a first bonding wire connecting the semiconductor chip to the first bonding pad, the first bonding wire contacting the first bonding pad and partially filling the first trench in order to connect bond pads and the active circuitry through various levels of metallization and enhances the strength of the bond between the wire and the bond pad. [0034-0036].
Regarding Claim 8, Kim in view of Ryan discloses the semiconductor package of claim 1, wherein
the at least one first alignment pattern (16, 17 above 14a) includes at least two first alignment patterns (See AK in Fig. 1) spaced apart from each other in the first direction (See direction of I-I and II-II of Fig. 2D) such that the first bonding pad is interposed between the at least two first alignment patterns. (See Fig. 1 of Kim)
Regarding Claim 9, Kim in view of Ryan discloses the semiconductor package of claim 1, further comprising:
a passivation layer (15) covering the upper surface of the substrate and covering side surfaces of the first bonding pad and the at least one first alignment pattern (See sides of 16 in contact with 15 in Fig. 2D), wherein
the first trench further extends toward the passivation layer such that an upper surface of the passivation layer has a step. (See Step in 15 in Fig. 2D)
Regarding Claim 10, Kim in view of Ryan discloses the semiconductor package of claim 1, further comprising:
a second bonding pad on a second upper pad, the second bonding pad including a second trench; (See 18b closest to a second 18A lower right corner Kim)
at least one second alignment pattern disposed on the at least one alignment pad such that the at least one second alignment pattern is adjacent to the second bonding pad; (See 18a closest to a second 18b lower right corner Kim)
Kim in view of Ryan as previously combined does not explicitly disclose a second bonding wire connecting the semiconductor chip to the second bonding pad.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor package in Kim in view of Ryan such that a second bonding wire connecting the semiconductor chip to the second bonding pad since it has been held that mere duplication of essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 and in order to connect a plurality of bond pads to active circuitry [0034]
Regarding Claim 11, Kim in view of Ryan discloses the semiconductor package of claim 10, wherein
the second trench extends in a direction parallel to the first direction. (Kim , Fig, 1 and 2)
Regarding Claim 14, Kim in view of Ryan discloses the semiconductor package of claim 10, wherein
the at least one first alignment pattern includes a plurality of first alignment patterns (lower left and lower right corners) such that the plurality of first alignment patterns are disposed farther from the semiconductor chip (C) than the first bonding pad. (18B) (Kim. Fig. 1)
Claim(s) 2, 3, 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over in Kim et al. (US 2008/0284048 A1) view of Ryan (US 2007/0134903 A1) and further in view of Hong (US 2014/0042633 A1).
Regarding Claim 2, Kim in view of Ryan discloses the semiconductor package of claim 1, wherein
the first bonding pad (16, 17 above 14b) includes a lower conductive layer (16), an intermediate conductive layer (17) sequentially stacked on the upper pad, and the at least one first alignment pattern (16, 17 above 14a) includes a lower material layer (16), an intermediate material layer (17) being sequentially stacked.( Kim Fig. 2)
Kim in view of Ryan does not explicitly disclose an upper conductive layer and an upper material layer
Hong (Fig. 8, 10) discloses an upper conductive layer (19b) and an upper material layer (19a) (See triple layer configuration (13, 15, 19) in Fig. 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package in Kim in view of Ryan and further in view of Hong such that the semiconductor package comprises an upper conductive layer and an upper material layer in order to increased contact area and have increased attaching strength [0051].
Regarding Claim 3, Kim in view of Ryan and Hong discloses the semiconductor package of claim 2, wherein
the lower material layer, the intermediate material layer, and the upper material layer, respectively, include a same material as the lower conductive layer, the intermediate conductive layer, and the upper conductive layer. (Hong Fig. 10)
Regarding Claim 5, Kim in view of Ryan and Hong discloses the semiconductor package of claim 2, wherein
a thickness of the intermediate conductive layer is within a range of 1 μm to 2 μm, and a thickness of the upper conductive layer is within a range of 1 μm to 2 μm.
Regarding Claim 6, Kim in view of Ryan discloses the semiconductor package of claim 1, wherein
the first bonding pad (16, 17 above 14b) includes a lower conductive layer (16) including a lower trench, an intermediate conductive layer (17) including an intermediate trench overlapping the lower trench (See Fig. 2),
Kim in view of Ryan does not explicitly disclose an upper conductive layer including the first trench, the first trench overlapping the intermediate trench.
Hong (Fig. 8, 10) discloses an upper conductive layer (19b) including a first trench, the first trench overlapping an intermediate trench.(See trenches in layers 13, 15 and 19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package in Kim in view of Ryan and further in view of Hong such that an upper conductive layer including the first trench, the first trench overlapping the intermediate trench in order to increased contact area and have increased attaching strength [0051].
Allowable Subject Matter
Claim 4, 7, 12, 13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 16 and 17 are allowed.
The following is an examiner's statement of reasons for allowance:
With regards to claim 16, none of the prior art teaches or suggests, alone or in combination, “a bonding wire connecting the chip pad to the bonding pad, the bonding wire including a stitch portion contacting the bonding pad and a wire portion between the stitch portion and the chip pad, wherein
the stitch portion includes a protrusion partially filling the trench, and a width of the at least one alignment pattern is within a range of 15 μm to 20 μm.” in the combination required by the claim.
Claims 17 are allowed by virtue of their dependency on the independent claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DMITRIY YEMELYANOV/Examiner, Art Unit 2891
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