DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 4, the limitation “a low-side power MOS region of the semiconductor die” renders the claim indefinite, as there is no antecedent basis for a semiconductor die. For purposes of examination the limitation will be interpreted as “a low-side power MOS region of a semiconductor die”. Claims 5-6 depend from and further limit claim 4 and are therefore correspondingly rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, and 12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lopez (U.S. PGPub 20230411262).
Regarding claim 1, Lopez teaches a substrate, comprising a plurality of metal layers that are sequentially stacked from the top downward and electrically interconnected, and the metal layers being spaced apart by dielectric layers (Figs. 6A-6H, [0059]-[0065]), the substrate having a low-side power connection region where metal strips in at least one of the metal layers extend in a direction different from a direction of extension of metal strips in another one of the metal layers extend ([0043], Fig. 6A, low-side region SN/GND, [0059]; Figs. 6G-6H, [0063]-[0064]).
Regarding claim 2, Lopez teaches wherein for each direction of extension, there are at least two of the metal layers, in which the metal strips extend in the specific direction of extension (Fig. 6A, [0059]; Figs. 6G-6H, [0063]-[0064]).
Regarding claim 4, Lopez teaches wherein the low-side power connection region is aligned in position with a low-side power MOS region of the semiconductor die, and wherein bumps in the low-side power MOS region are connected to metal strips in a topmost one of the metal layers in the low-side power connection region (Fig. 6A-Fig. 6B, [0060]; [0042]-[0043]).
Regarding claim 12, Lopez teaches the substrate of claim 1 and a semiconductor die flipped and mounted on the substrate ([0060], semiconductor die flip chip mounted on package substrate, [0035]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Michael (U.S. PGPub 20190341344) in view of Desai (U.S. Pat. 4407007).
Regarding claim 1, Michael teaches a substrate comprising a metal layer having a low-side power connection region with metal strips extending in a direction (Fig. 3, VSS, [0122]), but does not explicitly teach a plurality of metal layers sequentially stacked from the top downward and electrically interconnected, the metal layers being spaced apart by dielectric layers, where metal strips in at least one of the metal layers extend in a direction different from a direction of extension of metal strips in another one of the metal layers extend.
Desai teaches a multilayer substrate having metal layers spaced apart by dielectric layers, the substrate having a region where metal strips in at least one of the metal layers extend in a direction different from a direction of extension of metal strips in another one of the metal layers extend (col. 3, l. 65 – col. 4, l. 1-8).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Desai with Michael such that the substrate comprises a plurality of metal layers sequentially stacked from the top downward and electrically interconnected, the metal layers being spaced apart by dielectric layers, where metal strips in at least one of the metal layers extend in a direction different from a direction of extension of metal strips in another one of the metal layers extend for the purpose of controlling impedance and dispersing the voltage across the area of the substrate (Desai, col. 3, l. 65 – col. 4, l. 1-8).
Regarding claim 2, the combination of Michael and Desai teaches wherein for each direction of extension, there are at least two of the metal layers, in which the metal strips extend in the specific direction of extension (Desai, col. 3, l. 65 - col. 4, l. 1-8). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Desai for the reasons set forth in the rejection of claim 1.
Regarding claim 3, the combination of Michael and Desai teaches wherein the metal strips in any adjacent two of the metal layers extend in different directions (Desai, col. 3, l. 65 - col. 4, l. 1-8). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Desai for the reasons set forth in the rejection of claim 1.
Regarding claim 4, the combination of Michael and Desai teaches wherein the low-side power connection region is aligned in position with a low-side power MOS region of a semiconductor die, and wherein bumps in the low-side power MOS region are connected to metal strips in a topmost one of the metal layers in the low-side power connection region (Michael, Figs. 3-4, [0123]-[0124]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Desai for the reasons set forth in the rejection of claim 1.
Regarding claim 5, the combination of Michael and Desai teaches wherein a plurality of metal strips are arranged in the topmost metal layer in the low-side power connection region, and wherein bumps in each single column in the low-side power MOS region of the semiconductor die are connected to a single one of the metal strips in the topmost metal layer (Michael, Figs. 3-4, [0123]-[0124]; Fig. 6(a), [0132]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Desai for the reasons set forth in the rejection of claim 1.
Regarding claim 6, the combination of Michael and Desai teaches wherein columns of bumps in the low-side power MOS region electrically connected to any respective adjacent two of the metal strips in the topmost metal layer in the low-side power connection region belong to different functional networks (Michael, Figs. 3-4, [0123]-[0124]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Desai for the reasons set forth in the rejection of claim 1.
Regarding claim 7, the combination of Michael and Desai teaches wherein the plurality of metal layers comprise a first metal layer, a second metal layer, a third metal layer and a fourth metal layer, which are sequentially stacked from the top downward and electrically interconnected, wherein in the low-side power connection region, the metal strips in two of the first, second, third and fourth metal layers extend in a first direction, and the metal strips in the remaining two metal layers extend in a second direction different from the first direction (Desai, col. 3, l. 65 - col. 4, l. 1-8). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Desai for the reasons set forth in the rejection of claim 1.
Regarding claim 8, the combination of Michael and Desai teaches wherein the first direction is perpendicular to the second direction (Desai, col. 3, l. 65 - col. 4, l. 1-8). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Desai for the reasons set forth in the rejection of claim 1.
Regarding claim 9, the combination of Michael and Desai teaches wherein the direction of extension of the metal strips in the first metal layer is same to the direction a plurality of columns of bumps extend (Michael, Figs. 3-4, [0123]-[0124]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Desai for the reasons set forth in the rejection of claim 1.
Regarding claim 10, the combination of Michael and Desai teaches comprising a solder mask on a surface thereof close to the fourth metal layer, the solder mask provided therein with a plurality of elongated openings, in which the fourth metal layer is partially exposed, wherein in the low-side power connection region, the direction of extension of the metal strips in the fourth metal layer is the same as a direction of extension of the elongated openings (Michael, [0129], solder mask, [0123], lower portion of Fig. 3 shows elements that make direct external connection on bottom side of substrate; Desai, col. 3, l. 65 - col. 4, l. 1-8). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Desai for the reasons set forth in the rejection of claim 1.
Regarding claim 11, the combination of Michael and Desai teaches wherein in the low-side power connection region, the metal strips in the first metal layer extend in the first direction, the metal strips in the second metal layer extend in the second direction, the metal strips in the third metal layer extend in the first direction, and the metal strips in the fourth metal layer extend in the second direction (Desai, col. 3, l. 65 - col. 4, l. 1-8). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Desai for the reasons set forth in the rejection of claim 1.
Regarding claim 12, the combination of Michael and Desai teaches a package structure, comprising the substrate of claim 1 (see rejection of claim 1) and a semiconductor die flipped and mounted on the substrate (Michael, Fig. 6(a), [0132]; Desai, col. 2, l. 20-32). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Desai for the reasons set forth in the rejection of claim 1.
Regarding claim 13, the combination of Michael and Desai teaches wherein a front side of the semiconductor die faces toward the substrate and is provided thereon with a plurality of bumps, and wherein the semiconductor die has a low-side power MOS region, the low-side power MOS region is aligned in position with the low-side power connection region and provided therein with bumps connected to the metal strips in the topmost metal layer in the substrate in the low-side power connection region (Michael, Fig. 6(a), [0132]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Desai for the reasons set forth in the rejection of claim 1.
Regarding claim 14, the combination of Michael and Desai teaches wherein the bumps in the low-side power MOS region of the semiconductor die are arranged into a plurality of columns, wherein bumps of each single one of the columns belong to the same functional network, and wherein bumps of any adjacent two of the columns belong to different functional networks (Michael, Figs. 3-4, [0123]-[0124]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Desai for the reasons set forth in the rejection of claim 1.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Michael (U.S. PGPub 20190341344) in view of Desai (U.S. Pat. 4407007) and Katagiri (U.S. PGPub 20160027758).
Regarding claim 15, the combination of Michael and Desai teaches wherein the semiconductor die further has a high-side power MOS region and a control circuit region (Michael, [0011]-[0012], [0120]-[0121]), wherein bumps in the high-side power MOS region and the bumps in the low-side power MOS region have the same cross-sectional shape (Fig. 4, [0123]) but does not explicitly teach wherein the cross-sectional shape of the bumps in the high-side power MOS region or the cross-sectional shape of the bumps in the low-side power MOS region is different from a cross-sectional shape of bumps in the control circuit region.
Katagiri teaches bumps formed on a die, wherein bumps for electrical connections to power lines have a different size or shape from bumps for electrical connections to signal lines ([0059]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Katagiri with Michael and Desai such that the cross-sectional shape of the bumps in the high-side power MOS region or the cross-sectional shape of the bumps in the low-side power MOS region is different from a cross-sectional shape of bumps in the control circuit region for the purpose of improving the electrical properties for different uses (Katagiri, [0059]).
Conclusion
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/ALIA SABUR/Primary Examiner, Art Unit 2812