DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 4-6, 8, 10 and 12-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding independent claim 1, the limitation “characterized in being applied to a QFN package structure” does not comply with the written description requirement. The Specification states in the Background that QFN packages are “square or rectangular leadless surface-mount packages with a large exposed center pad on the bottom for thermal conduction and peripheral conductive pads surrounding the large pad for electrical connection”, and Fig. 1 depicts a conventional QFN package structure (Spec, p. 1).
See the attached schematic of a standard QFN package (from https://en.wikipedia.org/wiki/Flat_no-leads_package) compared with application Fig. 1 which shows a cross section through the peripheral conductive pads.
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The disclosed non-prior-art chip and substrate do not correspond to the definition provided of a QFN package, no reference or depiction of an exposed center pad is present and no further reference to thermal conduction is present. The bottom surface of the disclosed chip is shown in Fig. 3 and the bottom surface of the package substrate is shown in Fig. 9. The original disclosure does not describe the claim limitation sufficiently to convey that the inventor had possession of the claimed invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4-6, 8, 10 and 12-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding independent claim 1, the limitation “A substrate, characterized in being applied to a QFN package” renders the claim indefinite. It is unclear if a QFN package is being positively recited as part of the claim or if the substrate is supposed to be configured in some way that would make it suitable for a QFN package. It is further unclear what might be structurally required by the limitation due to the lack of reference to a QFN package or corresponding structural elements in the disclosure of the invention (see 112(a) rejection of claim 1). Additionally, the end of the preamble of the claim is not defined and cannot be identified. Therefore the bounds of the claims are indefinite and this limitation cannot be interpreted for purposes of examination.
Further, the limitation “a direction of extension of the metal strips … is the same as a direction defined by a plurality of columns of bumps in a low-side power MOS region of a semiconductor die” renders the claim indefinite, as it is unclear if the semiconductor die is being positively recited as part of the claim. For purposes of examination this limitation will be interpreted as “a low-side power MOS region of a semiconductor die bonded to the metal strips”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Michael (U.S. PGPub 20190341344) in view of Chen (U.S. PGPub 2010/0300732).
Regarding claim 1, Michael teaches a substrate comprising a first and second metal layer sequentially stacked from the top downward and electrically interconnected, the first and second metal layers being spaced apart by dielectric layers ([0115]-[0118], premolded substrate, two layers of conductive traces),
the substrate having a low-side power connection region wherein in the low-side power connection region, metal strips in the first metal layer extend in a first direction, wherein the plurality of metal strips are elongate in shape (Fig. 3, VSS, [0122]),
wherein a direction of extension of the metal strips in the first metal layer is the same as a direction defined by a plurality of columns of bumps in a low-side power MOS region of a semiconductor die (Figs. 3-4, [0123]-[0124]; Fig. 6(a), [0132]).
Michael does not explicitly teach third and fourth metal layers sequentially stacked downward from the second layer and spaced apart by dielectric layers, wherein metal strips in the third metal layer extend in the first direction, the metal strips in the second metal layer and in a fourth metal layer extend in a second direction different from the first direction and are elongate in shape.
Chen teaches a multilayer substrate having first, second, third, and fourth metal layers spaced apart by dielectric layers, wherein each layer is perpendicular to an adjacent layer and the metal strips are elongate in shape (Fig. 2, [0011]-[0012]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Chen with Michael such that third and fourth metal layers sequentially stacked downward from the second layer and spaced apart by dielectric layers, wherein metal strips in the third metal layer extend in the first direction, the metal strips in the second metal layer and in a fourth metal layer extend in a second direction different from the first direction and are elongate in shape for the purpose of providing power and signal layers with reduced crosstalk (Chen, [0012]).
Regarding claim 2, the combination of Michael and Chen teaches wherein for each direction of extension, there are at least two of the metal layers, in which the metal strips extend in the specific direction of extension (Chen, Figs. 1-2, [0012]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Chen for the reasons set forth in the rejection of claim 1.
Regarding claim 3, the combination of Michael and Chen teaches wherein the metal strips in any adjacent two of the metal layers extend in different directions (Chen, Figs. 1-2, [0012]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Chen for the reasons set forth in the rejection of claim 1.
Regarding claim 4, the combination of Michael and Chen teaches wherein the low-side power connection region is aligned in position with a low-side power MOS region of a semiconductor die, and wherein bumps in the low-side power MOS region are connected to metal strips in a topmost one of the metal layers in the low-side power connection region (Michael, Figs. 3-4, [0123]-[0124]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Chen for the reasons set forth in the rejection of claim 1.
Regarding claim 5, the combination of Michael and Chen teaches wherein a plurality of metal strips are arranged in the topmost metal layer in the low-side power connection region, and wherein bumps in each single column in the low-side power MOS region of the semiconductor die are connected to a single one of the metal strips in the topmost metal layer (Michael, Figs. 3-4, [0123]-[0124]; Fig. 6(a), [0132]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Chen for the reasons set forth in the rejection of claim 1.
Regarding claim 6, the combination of Michael and Chen teaches wherein columns of bumps in the low-side power MOS region electrically connected to any respective adjacent two of the metal strips in the topmost metal layer in the low-side power connection region belong to different functional networks (Michael, Figs. 3-4, [0123]-[0124]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Chen for the reasons set forth in the rejection of claim 1.
Regarding claim 7, the combination of Michael and Chen teaches wherein the plurality of metal layers comprise a first metal layer, a second metal layer, a third metal layer and a fourth metal layer, which are sequentially stacked from the top downward and electrically interconnected, wherein in the low-side power connection region, the metal strips in two of the first, second, third and fourth metal layers extend in a first direction, and the metal strips in the remaining two metal layers extend in a second direction different from the first direction (Chen, Figs. 1-2, [0012]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Chen for the reasons set forth in the rejection of claim 1.
Regarding claim 8, the combination of Michael and Chen teaches wherein the first direction is perpendicular to the second direction (Chen, Figs. 1-2, [0012]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Chen for the reasons set forth in the rejection of claim 1.
Regarding claim 9, the combination of Michael and Chen teaches wherein the direction of extension of the metal strips in the first metal layer is same to the direction a plurality of columns of bumps extend (Michael, Figs. 3-4, [0123]-[0124]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Chen for the reasons set forth in the rejection of claim 1.
Regarding claim 10, the combination of Michael and Chen teaches comprising a solder mask on a surface thereof close to the fourth metal layer, the solder mask provided therein with a plurality of elongated openings, in which the fourth metal layer is partially exposed, wherein in the low-side power connection region, the direction of extension of the metal strips in the fourth metal layer is the same as a direction of extension of the elongated openings (Michael, [0129], solder mask, [0123], lower portion of Fig. 3 shows elements that make direct external connection on bottom side of substrate; Chen, Figs. 1-2, [0012]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Chen for the reasons set forth in the rejection of claim 1.
Regarding claim 11, the combination of Michael and Chen teaches wherein in the low-side power connection region, the metal strips in the first metal layer extend in the first direction, the metal strips in the second metal layer extend in the second direction, the metal strips in the third metal layer extend in the first direction, and the metal strips in the fourth metal layer extend in the second direction (Chen, Figs. 1-2, [0012]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Chen for the reasons set forth in the rejection of claim 1.
Regarding claim 12, the combination of Michael and Chen teaches a package structure, comprising the substrate of claim 1 (see rejection of claim 1) and a semiconductor die flipped and mounted on the substrate (Michael, Fig. 6(a), [0132]; Chen, Figs. 1-2, [0012]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Chen for the reasons set forth in the rejection of claim 1.
Regarding claim 13, the combination of Michael and Chen teaches wherein a front side of the semiconductor die faces toward the substrate and is provided thereon with a plurality of bumps, and wherein the semiconductor die has a low-side power MOS region, the low-side power MOS region is aligned in position with the low-side power connection region and provided therein with bumps connected to the metal strips in the topmost metal layer in the substrate in the low-side power connection region (Michael, Fig. 6(a), [0132]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Chen for the reasons set forth in the rejection of claim 1.
Regarding claim 14, the combination of Michael and Chen teaches wherein the bumps in the low-side power MOS region of the semiconductor die are arranged into a plurality of columns, wherein bumps of each single one of the columns belong to the same functional network, and wherein bumps of any adjacent two of the columns belong to different functional networks (Michael, Figs. 3-4, [0123]-[0124]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Michael and Chen for the reasons set forth in the rejection of claim 1.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Michael (U.S. PGPub 20190341344) in view of Chen (U.S. PGPub 2010/0300732) and Katagiri (U.S. PGPub 20160027758).
Regarding claim 15, the combination of Michael and Chen teaches wherein the semiconductor die further has a high-side power MOS region and a control circuit region (Michael, [0011]-[0012], [0120]-[0121]), wherein bumps in the high-side power MOS region and the bumps in the low-side power MOS region have the same cross-sectional shape (Fig. 4, [0123]) but does not explicitly teach wherein the cross-sectional shape of the bumps in the high-side power MOS region or the cross-sectional shape of the bumps in the low-side power MOS region is different from a cross-sectional shape of bumps in the control circuit region.
Katagiri teaches bumps formed on a die, wherein bumps for electrical connections to power lines have a different size or shape from bumps for electrical connections to signal lines ([0059]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Katagiri with Michael and Chen such that the cross-sectional shape of the bumps in the high-side power MOS region or the cross-sectional shape of the bumps in the low-side power MOS region is different from a cross-sectional shape of bumps in the control circuit region for the purpose of improving the electrical properties for different uses (Katagiri, [0059]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALIA SABUR/Primary Examiner, Art Unit 2812
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