DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-6 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 4, the limitations "the low-side power MOS region of the semiconductor die" and “the bumps in the low-side power MOS region” render the claim indefinite, as there is no antecedent basis. For purposes of examination the limitation will be interpreted as "a low-side power MOS region of a semiconductor die comprising bumps". Claims 5-6 depend from and further limit claim 4 and are therefore correspondingly rejected.
Regarding claims 4-6 and 13, the amendment of “topmost” to “fourth” metal layer renders the claims indefinite, as claim 1 requires that the first through fourth layers are stacked sequentially from the top downward. The specification also depicts the top layer as the first metal layer that the die is connected to and the bottom layer as the fourth metal layer, see Fig. 2. For purposes of examination, in these claims, “fourth” will be interpreted as “first”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4-6, 10, and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (U.S. PGPub 2024/0194568) in view of Michael (U.S. PGPub 2019/0341344).
Regarding claim 1, Hwang teaches a substrate characterized in comprising a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer that are sequentially stacked from the top downward and electrically interconnected, the first, second, third and fourth metal layers being spaced apart by dielectric layers (Fig. 7, [0070]-[0083], L1-L4), the substrate having a low-side power connection region (Fig. 1, [0033]-[0034]), wherein in the low-side power connection region, metal strips in the first metal layer and the third metal layer extend in a first direction ([0072], [0076], Y direction), metal strips in the second metal layer extend in a second direction different from the first direction ([0074]), wherein the plurality of strips are elongate in shape (Fig. 7), wherein the first direction is perpendicular to the second direction, and wherein the metal layers in any adjacent two of the first, second, and third layers extend in different directions, such that for the first direction there are exactly two of the metal layers in which the metal strips extend in that direction.
Hwang does not explicitly teach in the embodiment of Fig. 7 wherein the fourth metal layer comprises metal strips extending in the second direction.
Hwang teaches wherein the lowest layer is not limited to the form of a plane ([0038]) and wherein adjacent layers are disposed in perpendicular directions ([0038]), and wherein the substrate is a package substrate ([0068]).
Michael teaches a substrate comprising a first metal layer, the substrate having a low-side power connection region wherein in the low-side power connection region, metal strips in the first metal layer extend in a first direction, wherein the plurality of metal strips are elongate in shape (Fig. 3, VSS, [0122]; Fig. 6, (d), [0132]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Michael with Hwang such that the fourth metal layer comprises metal strips extending in the second direction for the purpose of simplifying connection to a PCB (Michael, [0129]; Hwang, [0078]).
Regarding claim 4, the combination of Hwang and Michael teaches wherein the low-side power connection region is aligned in position with a low-side power MOS region of a semiconductor die comprising bumps, and wherein bumps in the low-side power MOS region are connected to metal strips in the first metal layer in the low-side power connection region (Hwang, [0038]-[0039]; Michael, Figs. 3-4, [0123]-[0124]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Hwang and Michael for the reasons set forth in the rejection of claim 1.
Regarding claim 5, the combination of Hwang and Michael teaches wherein a plurality of metal strips are arranged in the first metal layer in the low-side power connection region, and wherein bumps in each single column in the low-side power MOS region of the semiconductor die are connected to a single one of the metal strips in the first metal layer (Hwang, [0038]-[0039]; Michael, Figs. 3-4, [0123]-[0124]; Fig. 6(a), [0132]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Hwang and Michael for the reasons set forth in the rejection of claim 1.
Regarding claim 6, the combination of Hwang and Michael teaches wherein columns of bumps in the low-side power MOS region electrically connected to any respective adjacent two of the metal strips in the first metal layer in the low-side power connection region belong to different functional networks (Hwang, [0038]-[0039]; Michael, Figs. 3-4, [0123]-[0124]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Hwang and Michael for the reasons set forth in the rejection of claim 1.
Regarding claim 10, the combination of Hwang and Michael teaches comprising a solder mask on a surface thereof close to the fourth metal layer, the solder mask provided therein with a plurality of elongated openings, in which the fourth metal layer is partially exposed, wherein in the low-side power connection region, the direction of extension of the metal strips in the fourth metal layer is the same as a direction of extension of the elongated openings (Michael, [0129], solder mask, [0123], lower portion of Fig. 3 shows elements that make direct external connection on bottom side of substrate). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Hwang and Michael for the reasons set forth in the rejection of claim 1.
Regarding claim 12, the combination of Hwang and Michael teaches a package structure, comprising the substrate of claim 1 (see rejection of claim 1) and a semiconductor die flipped and mounted on the substrate (Hwang, Fig. 2; Michael, Fig. 6(a), [0132]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Hwang and Michael for the reasons set forth in the rejection of claim 1.
Regarding claim 13, the combination of Hwang and Michael teaches wherein a front side of the semiconductor die faces toward the substrate and is provided thereon with a plurality of bumps, and wherein the semiconductor die has a low-side power MOS region, the low-side power MOS region is aligned in position with the low-side power connection region and provided therein with bumps connected to the metal strips in the first metal layer in the substrate in the low-side power connection region (Hwang, [0038]-[0039]; Michael, Fig. 6(a), [0132]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Hwang and Michael for the reasons set forth in the rejection of claim 1.
Regarding claim 14, the combination of Hwang and Michael teaches wherein the bumps in the low-side power MOS region of the semiconductor die are arranged into a plurality of columns, wherein bumps of each single one of the columns belong to the same functional network, and wherein bumps of any adjacent two of the columns belong to different functional networks (Hwang, [0038]-[0039]; Michael, Figs. 3-4, [0123]-[0124]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Hwang and Michael for the reasons set forth in the rejection of claim 1.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang (U.S. PGPub 2024/0194568) in view of Michael (U.S. PGPub 2019/0341344) and Baello (U.S. PGPub 2019/0326245).
Regarding claim 15, the combination of Hwang and Michael teaches wherein the semiconductor die further has a high-side power MOS region and a control circuit region (Hwang, [0078], Michael, [0011]-[0012], [0120]-[0121]), wherein bumps in the high-side power MOS region and the bumps in the low-side power MOS region have the same cross-sectional shape (Michael, Fig. 4, [0123]) but does not explicitly teach wherein the cross-sectional shape of the bumps in the high-side power MOS region or the cross-sectional shape of the bumps in the low-side power MOS region is different from a cross-sectional shape of bumps in the control circuit region.
Baello teaches bumps formed on a die, wherein the bumps are formed with different shapes depending on the current that will be carried by the bump ([0041]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Baello with Hwang and Michael such that the cross-sectional shape of the bumps in the high-side power MOS region or the cross-sectional shape of the bumps in the low-side power MOS region is different from a cross-sectional shape of bumps in the control circuit region for the purpose of choosing appropriate bump features for different regions (Baello, [0041]).
Regarding claim 16, Baello teaches wherein the bumps are shaped like posts, and wherein bumps may be circular or elliptical (Figs. 7A-7B, [0041]). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to further combine the teachings of Baello with Hwang and Michael such that the bumps in the high-side power region, the bumps in the low-side power region, and the bumps in the control circuit region are all shaped like posts, the bumps in the high-side power MOS region and the low-side power MOS region all have an elliptical cross-section, and wherein the bumps in the control circuit region all have a circular cross section for the reasons set forth in the rejection of claim 14.
Regarding claim 17, the combination of Hwang, Michael, and Baello teaches wherein the ellipse has a minor axis oriented defined by the columns of bumps (Baello, Fig. 11, [0046]) and ranging from 50-200 um and a major axis ranging from 100-400 um, and wherein the circle has a diameter ranging from 50-150 um. In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists. See MPEP 2144.05. Therefore it would have been obvious to a person having ordinary skill in the art to further combine the teachings of Hwang, Michael, and Baello such that the ellipse has a minor axis ranging from 70-130 um, a major axis ranging from 94-176 um, and the circle has a diameter ranging form 70-130 um.
Conclusion
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/ALIA SABUR/Primary Examiner, Art Unit 2812
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