DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species C in the reply filed on 7/10/2026 is acknowledged.
Claims 2, 10-11, 16-17 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/10/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-9, 12-15 and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hong et al (US 2022/0109046; hereinafter Hong).
Regarding claim 1, Figs 3C-3E and 5B of Hong discloses a semiconductor device comprising:
a stacked transistor structure (Fig 3C) including a column having field effect transistors (301/302; Fig 3C; ¶ [0050]) on at least two levels in the column, the at least two levels including a top tier (Fig 3C) and bottom tier (Fig 3C) and
first channels (320; Fig 3C; ¶ [0050]) of a first field effect transistor (302; Fig 3C; ¶ [0050]) disposed on a first side (top side; Fig 3C) of the column at the top tier (Fig 3C) and second channels (310; Fig 3C; ¶ [0050]) of a second field effect transistor (301; Fig 3C; ¶ [0050]) disposed on a second side (Bottom side; Fig 3C) of the column opposite the first side (top side; Fig 3C) at the bottom tier to form an offset (Fig 3C) between the first channels (320; Fig 3C; ¶ [0050]) and the second channels (310; Fig 3C; ¶ [0050]) within the column.
Regarding claim 3, Figs 3C-3E and 5B of Hong discloses the first channels (320; Fig 3C; ¶ [0050]) and the second channels (310; Fig 3C; ¶ [0050]) have different sizes (Fig 3C).
Regarding claim 4, Figs 3C-3E and 5B of Hong discloses the first field effect transistor (302; Fig 3C; ¶ [0050]) includes a source/drain region (313/314; Figs 3D-3E; ¶ [0063]) which is offset (Figs 3D-3E) from a source/drain region (311/312; Figs 3D-3E; ¶ 321[0063]) of the second field effect transistor (301; Fig 3C; ¶ [0050]) within the column.
Regarding claim 5, Figs 3C-3E and 5B of Hong discloses at least one opposite connection contact (321/322/323; Fig 3D; ¶ [0063]) disposed within the column (Fig 3D) through one of the at least two levels to connect to a source/drain region (313/314/311/312; Figs 3D-3E; ¶ [0063]) in another one of the at least two levels.
Regarding claim 6, Figs 3C-3E and 5B of Hong discloses the at least one opposite connection (321/322/323; Fig 3D; ¶ [0063]) includes two opposite connections (321/322/323; Fig 3D; ¶ [0063]) within the column.
Regarding claim 7, Figs 3C-3E and 5B of Hong discloses the first field effect transistor (302; Fig 3C; ¶ [0050]) includes a tri-gate field effect transistor (Figs 2 and 3; Since Figs 2 and 3 shows gate structure (225) wraps around three sides of a fin-shaped channel. Therefore Hong discloses first field effect transistor is a tri-gate field effect transistor).
Regarding claim 8, Figs 3C-3E and 5B of Hong discloses the offset (Fig 3D) provides overlap (Fig 3D) between the first channels (320; Fig 3C; ¶ [0050]) and the second channels (310; Fig 3C; ¶ [0050]) within their respective levels of the at least two levels in the column. (Fig 3D)
Regarding claim 9, Figs 3C-3E and 5B of Hong discloses the offset (Fig 3D) is large enough to prevent overlap between the first channels (320; Fig 3C; ¶ [0050]) and the second channels (310; Fig 3C; ¶ [0050]) within their respective levels of the at least two levels in the column.
Regarding claim 12, Figs 3C-3E and 5B of Hong discloses a semiconductor device comprising:
a stacked transistor structure (Fig 3C) including a column having tri-gate field effect transistors (301/302; Fig 3C; ¶ [0050]) on at least two levels in the column, the at least two levels including a top tier (Fig 3C) and bottom tier (Fig 3C) and
a first tri-gate field effect transistor (302; Fig 3C; ¶ [0050]) disposed on a first side of the column at the top tier (Fig 3C) and a second tri-gate field effect transistor (301; Fig 3C; ¶ [0050]) offset from the first tri-gate field effect transistor (302; Fig 3C; ¶ [0050]) on a second side of the column opposite the first side at the bottom tier (Fig 3D) within the column,
at least one opposite connection contact (321/322/323; Fig 3D; ¶ [0063]) disposed within the column, the at least one opposite connection passing through the column to connect to one of the first and second tri-gate field effect transistors (Figs 3D-3E). (Figs 2 and 3; Since Figs 2 and 3 shows gate structure (225) wraps around three sides of a fin-shaped channel. Therefore Hong discloses first field effect transistor is a tri-gate field effect transistor).
Regarding claim 13, Figs 3C-3E and 5B of Hong discloses the first tri-gate field effect transistor (302; Fig 3C; ¶ [0050]) and the second tri-gate field effect transistor (301; Fig 3C; ¶ [0050]) each includes gates (215/225; Fig 2B; ¶ [0041]) with gate conductors that surrounds three sides of device channels (Fig 2).
Regarding claim 14, Figs 3C-3E and 5B of Hong discloses the gates have different sizes (Figs 2, 3C-3E).
Regarding claim 15, Figs 3C-3E and 5B of Hong discloses the device channels (310/320; Fig 3C; ¶ [0050]) of the first tri-gate field effect transistor (302; Fig 3C; ¶ [0050]) and the second tri-gate field effect transistor (301; Fig 3C; ¶ [0050]) have different sizes (Fig 3D).
Regarding claim 18, Figs 3C-3E and 5B of Hong discloses the at least one opposite connection (321/322/323; Fig 3D; ¶ [0063]) includes two opposite connections (321/322/323; Fig 3D; ¶ [0063]) within the column.
Regarding claim 19, Figs 3C-3E and 5B of Hong discloses the at least one opposite connection (321/322/323; Fig 3D; ¶ [0063]) connects to a source drain region (313/314; Figs 3D-3E; ¶ [0063]) of one of the first and second tri-gate field effect transistors.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hong et al (US 2022/0367520)
Lilak et al (US 2020/0098756)
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
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