DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-14 & 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20140124956) in view of Kang (US 20200251447).
Regarding claim 1, Lee discloses that a semiconductor package, comprising:
a first chip stack including first semiconductor chips 31, the first semiconductor chips 31 on a substrate 11 and having an offset stack structure (Fig. 2e);
a second chip stack 31 on the substrate and horizontally spaced apart from the first chip stack 31, the second chip stack including second semiconductor chips 31, the second semiconductor chips 31 having an offset stack structure (Fig. 2e);
a first buffer chip 85b on the substrate 11 and at a side of the first chip stack 31;
a second buffer chip 85b on the substrate 11 and at a side of the second chip stack (Fig. 2e);
a connection substrate on the first and second chip stacks 60 & 13;
a first mold layer covering the substrate, the first chip stack, and the second chip stack (para. 0101).
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Lee fails to teach that the first mold layer exposing a top surface of the connection substrate and a third chip stack including third semiconductor chips , the third semiconductor chips on the first mold layer and a fourth chip stack on the first mold layer and horizontally spaced apart from the third chip stack, the fourth chip stack including fourth semiconductor chips, the fourth semiconductor chips having an offset stack structure; and a second mold layer covering the first mold layer, the third chip stack, and the fourth chip stack.
However, Kang suggests that a stacking chips including the first mold layer 120 exposing a top surface of the connection substrate 124 and a third chip stack 310 including third semiconductor chips (Fig. 1A), the third semiconductor chips 130 on the first mold layer.
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Lee with a stacking chips including the first mold layer exposing a top surface of the connection substrate and a third chip stack including third semiconductor chips, the third semiconductor chips on the first mold layer as taught by Kang in order to enhance complexity of chip process with various stacking chips and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
The combination of Lee & Kang disclose that a fourth chip stack on the first mold layer and horizontally spaced apart from the third chip stack, the fourth chip stack including fourth semiconductor chips, the fourth semiconductor chips having an offset stack structure; and a second mold layer covering the first mold layer, the third chip stack, and the fourth chip stack (additional Lee’s chip with Kang’s stacking method).
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Reclaim 2, Lee & Kang disclose that a number of each of the first to fourth semiconductor chips is eight (Fig. 2e, Lee).
Reclaim 3, Lee & Kang disclose that each of the first to fourth semiconductor chips comprises a chip pad on a top surface thereof, the semiconductor package further comprises first to fourth wires, each of the first to fourth wires connected to the chip pad of a corresponding one of the first to fourth semiconductor chips, the first wire connects the chip pad of a lowermost one of the first semiconductor chips to the substrate, the second wire connects the chip pad of a lowermost one of the second semiconductor chips to the substrate, the third wire connects the chip pad of a lowermost one of the third semiconductor chips to the substrate, and the fourth wire connects the chip pad of a lowermost one of the fourth semiconductor chips to the substrate (Lee, Fig. 2e in view of Kang’s Fig. 1A).
Reclaim 4, Lee & Kang disclose that end portions of the third and fourth wires are exposed to an outside at a bottom surface of the second mold layer, the semiconductor package further comprises, a fifth wire disposed in the first mold layer to connect the third wire to the substrate, and a sixth wire disposed in the first mold layer to connect the fourth wire to the substrate (Lee, Fig. 2e in view of Kang’s Fig. 1A).
Reclaim 5, Lee & Kang disclose that a seventh wire in the first mold layer and connected to the first buffer chip, the seventh wire having an end portion exposed to an outside at a top surface of the first mold layer; and an eighth wire in the first mold layer and connected to the second chip, the eighth wire having an end portion exposed to an outside at the top surface of the first mold layer (Lee, Fig. 2e in view of Kang’s Fig. 1A).
Reclaim 6, Lee & Kang disclose that a ninth wire in the second mold layer, the ninth wire connecting the chip pad on one of the third semiconductor chips to the seventh wire; and a tenth wire in the second mold layer, the tenth wire connecting the chip pad on one of the fourth semiconductor chips to the eighth wire, wherein the seventh wire has a first circular section on the top surface of the first mold layer, the first circular section having a first diameter, the eighth wire has a second circular section on the top surface of the first mold layer, the second circular section having a second diameter, the ninth wire is in contact with the seventh wire and has a first end portion, the first end portion having an elliptical shape with long and short axes, and the tenth wire is in contact with the eighth wire and has a second end portion, the second end portion having an elliptical shape with long and short axes (Lee, Fig. 2e in view of Kang’s Fig. 1A).
Reclaim 7, Lee & Kang disclose that the connection substrate comprises a bare silicon wafer, an organic substrate, or an organic film, and a thickness of the connection substrate ranges from 5 µm to 30 µm (Lee, Fig. 2e in view of Kang’s Fig. 1A).
Reclaim 8, Lee & Kang disclose that a first adhesive layer between a lowermost one of the first semiconductor chips and the substrate, the first adhesive layer having a first thickness; and a second adhesive layer between the first semiconductor chips, the second adhesive layer having a second thickness, wherein the first thickness is larger than the second thickness (Lee, Fig. 2e in view of Kang’s Fig. 1A).
Reclaim 9, Lee & Kang disclose that a third adhesive layer between a lowermost one of the third semiconductor chips and the first mold layer, the third adhesive layer having a third thickness; and a fourth adhesive layer between the third semiconductor chips, the fourth adhesive layer having a fourth thickness (Lee, Fig. 2e in view of Kang’s Fig. 1A).
Reclaim 10, Lee & Kang disclose that a fifth adhesive layer between the connection substrate and the first chip stack, the fifth adhesive layer having a fifth thickness, wherein the fifth thickness is equal to at least one of the first thickness or the third thickness (Lee, Fig. 2e in view of Kang’s Fig. 1A).
Reclaim 11, Lee & Kang disclose that the first, third, and fifth thicknesses range from 20 µm to 40 µm, and the second thickness and fourth thickness range from 5 µm to 20 µm (Lee, Fig. 2e in view of Kang’s Fig. 1A).
Reclaim 12, Lee & Kang disclose that the first and second mold layers include materials different from each other (Lee, Fig. 2e in view of Kang’s Fig. 1A).
Reclaim 13, Lee & Kang disclose that a mechanical strength of the first mold layer is larger than a mechanical strength of the second mold layer (Lee, Fig. 2e in view of Kang’s Fig. 1A).
Reclaim 14, Lee & Kang disclose that an edge of a top surface of the first mold layer has a stepwise structure, and a bottom surface of the second mold layer is fittingly engaged with the top surface of the first mold layer (Lee, Fig. 2e in view of Kang’s Fig. 1A).
Regarding claim 16, Lee & Kang disclose that a semiconductor package, comprising:
a first chip stack 31 including first semiconductor chips, the first semiconductor chips on a substrate and having an offset stack structure;
a second chip stack 31 including second semiconductor chips, the second semiconductor chips on the first chip stack and having an offset stack structure;
a first buffer chip 85a/b on the substrate 11 and at a side of the first chip stack (Lee, Fig. 2e);
a second buffer chip 85b/a on the substrate 11 and at an opposite side of the first chip stack;
a connection substrate 11 on the second chip stack;
a first mold layer covering the substrate, the first chip stack, and the second chip stack, the first mold layer exposing a top surface of the connection substrate (para. 0101);
a third chip stack including third semiconductor chips, the third semiconductor chips on the first mold layer and having an offset stack structure; a fourth chip stack including fourth semiconductor chips, the fourth semiconductor chips on the third chip stack and having an offset stack structure; and a second mold layer covering the first mold layer, the third chip stack, and the fourth chip stack (Lee’s Fig. 2e in view of Kang’s stacking method in Fig. 1A).
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Reclaim 17, Lee & Kang disclose that each of the first to fourth semiconductor chips comprises a chip pad on a top surface thereof, the semiconductor package further comprises first to fourth wires, each of the first to fourth wires connected to the chip pad of a corresponding one of the first to fourth semiconductor chips, the first wire connects the chip pad of a lowermost one of the first semiconductor chips to the substrate, the second wire connects the chip pad of a lowermost one of the second semiconductor chips to the substrate, the third wire connects the chip pad of a lowermost one of the third semiconductor chips to the substrate, and the fourth wire connects the chip pad of a lowermost one of the fourth semiconductor chips to the substrate (Lee’s Fig. 2e in view of Kang’s stacking method in Fig. 1A).
Reclaim 18, Lee & Kang disclose that end portions of the third and fourth wires are exposed to an outside at a bottom surface of the second mold layer, the semiconductor package further comprises, a fifth wire in the first mold layer and connecting the third wire to the substrate, and a sixth wire in the first mold layer and connecting the fourth wire to the substrate (Lee’s Fig. 2e in view of Kang’s stacking method in Fig. 1A).
Reclaim 19, Lee & Kang disclose that a seventh wire in the first mold layer and connected to the first buffer chip, the seventh wire having an end portion exposed to an outside at a top surface of the first mold layer; and an eighth wire in the first mold layer and connected to the second chip, the eighth wire having an end portion exposed to an outside at the top surface of the first mold layer (Lee’s Fig. 2e in view of Kang’s stacking method in Fig. 1A).
Reclaim 20, Lee & Kang disclose that a ninth wire in the second mold layer, the ninth wire connecting the chip pad one of the third semiconductor chips to the seventh wire; and a tenth wire in the second mold layer, the tenth wire connecting the chip pad of one of the fourth semiconductor chips to the eighth wire (Lee’s Fig. 2e in view of Kang’s stacking method in Fig. 1A).
Allowable Subject Matter
Claim 15 is allowed over Lee in view of Kang.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
After further search and consideration, the prior art neither anticipated nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination.
The prior art does not teach or render obvious “ - - the first wire connects the chip pad of a lowermost one of the first semiconductor chips to the substrate, the second wire connects the chip pad of a lowermost one of the second semiconductor chips to the substrate, the third wire connects the chip pad of a lowermost one of the third semiconductor chips to the substrate, the fourth wire connects the chip pad of a lowermost one of the fourth semiconductor chips to the substrate, and end portions of the third and fourth wires are exposed to an outside at a bottom surface of the second mold layer, and wherein the semiconductor package further comprises a fifth wire in the first mold layer and connecting the third wire to the substrate, a sixth wire in the first mold layer and connecting the fourth wire to the substrate, a seventh wire in the first mold layer and connected to the first buffer chip, the seventh wire having an end portion exposed to an outside at a top surface of the first mold layer, an eighth wire in the first mold layer and connected to the second buffer chip, the eighth wire having an end portion exposed to an outside at the top surface of the first mold layer, a ninth wire in the second mold layer and connecting the chip pad of one of the third semiconductor chips to the seventh wire, and a tenth wire in the second mold layer and connecting the chip pad of one of the fourth semiconductor chips to the eighth wire. ” with combination of the other limitations as recited in claim 15.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/SU C KIM/Primary Examiner, Art Unit 2899