DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8, 10-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S., Publication No. 2021/0057363) in view of Shi et al. (U.S. Publication No. 2021/0167171).
Regarding claim 1, Chen teaches a semiconductor device comprising:
an insulating structure (Fig. 17, insulating structure 108/114) on a semiconductor substrate (substrate 102);
lower conductive patterns (patterns 112) in the insulating structure (Fig. 17);
upper conductive patterns (upper patterns 118) on the insulating structure (Fig. 17);
conductive vias (vias not individually labeled, but see Fig. 17, vias connect 118 to 112 through layer 114) in the insulating structure and connecting at least one of the upper conductive patterns to at least one of the lower conductive patterns (Fig. 11);
an etch stop layer (etch stop 120) covering the protective layer (covering patterns 118, see below discussion of protecting layer);
a first passivation layer (passivation layer 122) between the upper conductive patterns and on the etch stop layer (Fig. 17); and
an upper passivation layer (upper passivation layer 126) on the first passivation layer (Fig. 17).
Chen does not teach a protective layer covering the insulating structure and the upper conductive patterns. However, Shi teaches a similar device in which there is a protective layer between the conductive patterns and the etch stop layer (Shi Fig. 1, protective layer 28 between conductive pattern 24 and etch stop layer 34). It would have been obvious to a person of skill in the art at the time of the effective filing date that a protective layer could have been formed between the conductive patterns and etch stop because this allows for protection of the interconnect layers prior to further processing steps, such as etching for formation of through vias (see Shi Fig. 2-3 and paragraph [0025]).
Regarding claim 2, Chen in view of Shi teaches the semiconductor device of claim 1, wherein an upper surface of the first passivation layer is coplanar with an upper end of the etch stop layer (Chen Fig. 17).
Regarding claim 3, Chen in view of Shi teaches the semiconductor device of claim 1, further comprising:
a second passivation layer between the etch stop layer and the upper passivation layer (see Chen Fig. 11, second passivation layer 124 can be between etch stop 120 and upper passivation layer 126), wherein the first passivation layer is surrounded by the etch stop layer and the second passivation layer (see Chen Fig. 11).
Regarding claim 4, Chen in view of Shi teaches the semiconductor device of claim 1, wherein the etch stop layer has a first thickness and a second thickness, thicker than the first thickness (see Chen Fig. 14, paragraph [0036]-[0037], ESL thickness of top of conductive patterns is 100-500 A, and thickness of sidewalls and bottom is 500-1500 A).
Regarding claim 5, Chen in view of Shi teaches the semiconductor device of claim 4, wherein the etch stop layer comprises a first portion vertically overlapping the upper conductive patterns (Chen Fig. 14, portion on top of patterns 118), and a second portion vertically overlapping the first passivation layer (Chen Fig. 14, portion not on top of patterns 118),
wherein the first portion has the first thickness, and the second portion has the second thickness (see Chen Fig. 14 and paragraph [0036][-0037]).
Regarding claim 7, Chen in view of Shi teaches the semiconductor device of claim 1, wherein the upper passivation layer is in contact with an upper surface of the first passivation layer (see Chen Fig. 17).
Regarding claim 8, Chen in view of Shi teaches the semiconductor device of claim 7, further comprising:
an oxide layer between the etch stop layer and the upper passivation layer (see Chen Fig. 18, paragraph [0029]), layer 124 can be an oxide layer).
Regarding claim 10, Chen in view of Shi teaches the semiconductor device of claim 1, wherein a thickness of each of the upper conductive patterns is 1 um to 4 um (see Chen paragraph [0025]).
Regarding claim 11, Chen in view of Shi teaches the semiconductor device of claim 1, wherein a thickness of the first passivation layer is 1.5 pm to 3 pm (see Chen paragraph [0025] and [0026], thickness of passivation layer 122 is thickness of 118 – thickness of 120).
Regarding claim 12, Chen in view of Shi teaches the semiconductor device of claim 1, wherein a thickness of the etch stop layer is 0.1 um or less (see Chen paragraph [0026]).
Regarding claim 13, Chen in view of Shi teaches the semiconductor device of claim 1, further comprising:
a via pad below the semiconductor substrate, and
a through-electrode connected to the via pad and passing through the semiconductor substrate.
Shi teaches a via pad (Shi Fig. 14, via pad 54) below the semiconductor substrate (Shi Fig. 14), and a through-electrode (Shi Fig. 14, through electrode 40A) connected to the via pad and passing through the semiconductor substrate (Fig. 14). It would have been obvious to a person of skill in the art at the time of the effective filing date that a via pad and through electrode could have been included in the device of Chen because this allows for stacking dies with connections between each die in the stack.
Regarding claim 15, Chen in view of Shi teaches the semiconductor device of claim 1, wherein the etch stop layer comprises a material different from a material of the protective layer and a material of the first passivation layer (Shi paragraph [0026], protective layer is SiON; paragraph [0026], ESL is SiN; paragraph [0026], passivation layer is SiO2).
Claims 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Shi, further in view of Kim et al. (U.S. Patent No. 6,484,300).
Regarding claim 6, Chen in view of Shi teaches the semiconductor device of claim 1, but does not teach wherein an upper surface of the first passivation layer comprises a curved surface,
at least a portion of the upper surface of the first passivation layer is on a lower level than an upper end of the etch stop layer.
However, Kim teaches that when an interconnect which has dielectric formed over it is planarized, a phenomenon known as dishing occurs, which reduces the dielectric layer in below the level of the interconnects in a concave, curved pattern (see Kim Fig. 2A-2B). It would have been obvious to a person of skill in the art at the time of the effective filing date that dishing could have occurred to the passivation layer of Chen because Kim teaches that this is a common side effect of CMP process, which Chen uses (Chen paragraph [0026]).
Regarding claim 9, Chen in view of Shi teaches the semiconductor device of claim 7, but does not teach wherein the upper surface of the first passivation layer comprises a curved surface, and
an upper surface of a portion of the upper passivation layer vertically overlapping the first passivation layer is a curved surface.
However, Kim teaches that when an interconnect which has dielectric formed over it is planarized, a phenomenon known as dishing occurs, which reduces the dielectric layer in below the level of the interconnects in a concave, curved pattern (see Kim Fig. 2A-2B). Because the upper passivation layer of Chen is formed over the passivation layer, it would also have a curved surface to match the curved surface of the bottom passivation layer. It would have been obvious to a person of skill in the art at the time of the effective filing date that dishing could have occurred to the passivation layer of Chen because Kim teaches that this is a common side effect of CMP process, which Chen uses (Chen paragraph [0026]).
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Shi, further in view of Kim et al. (U.S. Publication No. 2019/0221520)(“Kim2”)
Regarding claim 16, Chen teaches a semiconductor package comprising:
wherein one or more of the semiconductor devices includes,
a semiconductor substrate (Fig. 17, substrate 102),
an insulating structure (108/114) on an upper surface of the semiconductor substrate (Fig. 17),
upper conductive patterns (patterns 118) on the insulating structure,
an etch stop layer (ESL 120) covering the protective layer (Fig. 17),
a first passivation layer (122) between the upper conductive patterns and on the etch stop layer (Fig. 17),
an upper passivation layer (126) on the first passivation layer, and
a connection pad (connection pad 128) connected to one of the upper conductive patterns (Fig. 17).
Chen does not teach a via pad on a lower surface of the semiconductor substrate, a through-electrode connected to the via pad and passing through the semiconductor substrate, and a protective layer covering the insulating structure and the upper conductive patterns. However, However, Shi teaches a similar device in which there is a protective layer between the conductive patterns and the etch stop layer (Shi Fig. 1, protective layer 28 between conductive pattern 24 and etch stop layer 34); and a via pad (Shi Fig. 14, via pad 54) below the semiconductor substrate (Shi Fig. 14), and a through-electrode (Shi Fig. 14, through electrode 40A) connected to the via pad and passing through the semiconductor substrate (Fig. 14). It would have been obvious to a person of skill in the art at the time of the effective filing date that a protective layer could have been formed between the conductive patterns and etch stop because this allows for protection of the interconnect layers prior to further processing steps, such as etching for formation of through vias (see Shi Fig. 2-3 and paragraph [0025]). It would have also been obvious to a person of skill in the art at the time of the effective filing date that a via pad and through electrode could have been included in the device of Chen because this allows for stacking dies with connections between each die in the stack.
Chen in view of Shi does not teach a plurality of semiconductor devices sequentially stacked on a buffer chip; an adhesive layer between the plurality of semiconductor devices; and an encapsulant covering the buffer chip and the plurality of semiconductor devices. However, Kim2 teaches a package including a plurality of semiconductor devices (Kim2 Fig. 1, dies 120) sequentially stacked on a buffer chip (buffer 110); an adhesive layer (Kim2 Fig. 1, adhesive 130) between the plurality of semiconductor devices; and an encapsulant covering the buffer chip and the plurality of semiconductor devices (Kim2 Fig. 1, encapsulant 140). It would have been obvious to a person of skill in the art at the time of the effective filing date that the generic chips of Chen in view of Shi could have been memory chips stacked over a buffer chip because this is a common use of chips to create high bandwidth memory.
Regarding claim 17, Chen in view of Shi and Kim2 teaches the semiconductor package of claim 16, wherein the connection pad passes through the protective layer, the etch stop layer, and the upper passivation layer (see Chen Fig. 17 and Shi Fig. 1).
Claims 14, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Shi, further in view of Choi et al. (U.S. Publication No. 2021/0305115).
Regarding claim 14, Chen in view of Shi teaches the semiconductor device of claim 1, wherein the semiconductor substrate comprises an element region, an edge region surrounding the element region, and a cutting region surrounding the edge region, and the etch stop layer extends to the edge region and the cutting region and covers a side surface of the insulating structure.
However, Choi teaches the semiconductor substrate comprises an element region (Choi Fig. 10, element region 10), an edge region surrounding the element region (Choi Fig. 10, edge region 24), and a cutting region surrounding the edge region (Choi Fig. 10, cutting region 22). Shi teaches that the etch stop layer extends to a similar trench to that formed by Choi (see Shi Fig. 12, trench at 32 is analogous to trench of Choi) and covers a side surface of the insulating structure (Shi Fig. 12, ESL 34 covers side of insulating structure 16). It would have been obvious to a person of skill in the art at the time of the effective filing date that the ESL covering a sidewall of a trench through the interconnect/substrate layers, as taught by Shi, could have also been used to cover the sidewalls of the interconnect/substrate trench of Choi, because this allows for protection of the sidewalls by the etch stop layer.
Regarding claim 18, Chen teaches a semiconductor device comprising:
a semiconductor substrate (Fig. 21, substrate 102) including a device region (region where active components are, see paragraph [0014]),
an insulating structure (insulating structure 108/114) on the semiconductor substrate, the insulating structure including a first upper insulating layer (110), a second upper insulating layer (110), and a third upper insulating layer (114) that are sequentially stacked (Fig. 21);
lower conductive patterns (patterns 112) in the first upper insulating layer (Fig. 21);
a first upper conductive pattern (118) and a second upper conductive pattern (also labeled 118) on the insulating structure;
conductive vias (vias through 114 not labeled, vias 113) passing through the second upper insulating layer and the third upper insulating layer (Fig. 21), the conductive vias connecting the first upper conductive pattern to at least one of the lower conductive patterns (Fig. 21, connection not specifically shown, but inherent that 118 connects through the RDL 108 in order to have functionality); and
a passivation structure (passivation structure 122/120) on the insulating structure, the first upper conductive pattern, and the second upper conductive pattern (Fig. 21), the passivation structure including an opening exposing the first upper conductive pattern (Fig. 21, opening at 133A),
wherein the passivation structure includes:
an etch stop layer (etch stop 120) covering the protective layer,
a first passivation layer (122) between the first upper conductive pattern and the
second upper conductive pattern and on the etch stop layer (Fig. 21),
a second passivation layer (second passivation layer 124) covering the etch stop layer and the first passivation layer (Fig. 21), and
an upper passivation layer (upper passivation layer 126) on the second passivation layer.
Chen does not teach a protective layer covering the first upper conductive pattern and the second upper conductive pattern. However, Shi teaches a similar device in which there is a protective layer between the conductive patterns and the etch stop layer (Shi Fig. 1, protective layer 28 between conductive pattern 24 and etch stop layer 34). It would have been obvious to a person of skill in the art at the time of the effective filing date that a protective layer could have been formed between the conductive patterns and etch stop because this allows for protection of the interconnect layers prior to further processing steps, such as etching for formation of through vias (see Shi Fig. 2-3 and paragraph [0025]).
Chen in view of Shi does not teach an edge region surrounding the device region, and a cutting region surrounding the edge region. However, Choi teaches a similar device which includes an edge region surrounding the device region (Choi Fig. 2, edge region 24) and a cutting region surrounding the edge region (Choi cutting region 22). It would have been obvious to a person of skill in the art at the time of the effective filing date that the device of Chen in view of Shi could have included an edge and cutting region because this allows for multiple dies to be created on one wafer and subsequently cut into individual dies.
Regarding claim 19, Chen in view of Shi and Choi teaches the semiconductor device of claim 18, wherein the etch stop layer defines a trench along the cutting region and is in contact with a side surface of the insulating structure and a side surface of the protective layer.
Shi teaches that the etch stop layer extends to a similar trench to that formed by Choi (see Shi Fig. 12, trench at 32 is analogous to trench of Choi) and covers a side surface of the insulating structure (Shi Fig. 12, ESL 34 covers side of insulating structure 16). It would have been obvious to a person of skill in the art at the time of the effective filing date that the ESL covering a sidewall of a trench through the interconnect/substrate layers, as taught by Shi, could have also been used to cover the sidewalls of the interconnect/substrate trench of Choi, because this allows for protection of the sidewalls by the etch stop layer.
Regarding claim 20, Chen in view of Shi and Choi teaches the semiconductor device of claim 18, wherein a lower surface of the first passivation layer is on a higher level than a lower surface of the first upper conductive pattern (see Chen Fig. 21), and
an upper surface of the first passivation layer is on a higher level than an upper surface of the first upper conductive pattern (Chen Fig. 21).
Conclusion
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/EVAN G CLINTON/ Primary Examiner, Art Unit 2899
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