DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) submitted on December 11, 2023 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 14-17 and 19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0113193 A1 (hereinafter “Li”).
Regarding claim 14, Li discloses in Fig. 1A and related text a semiconductor device (a field effect transistor (FET); [0047]) comprising:
a gate structure (243; [0061]) extending in one direction (vertical direction);
a source/drain region (239 (the one on the right); [0047]) outside of the gate structure; and
a backside contact plug (265, 265A; [0024] and [0059]) below the source/drain region, having a second central axis (the vertical dashed line on the left) offset in a horizontal direction from a first central axis (the vertical dashed line on the right) of the source/drain region, and connected to the source/drain region,
wherein the backside contact plug includes a vertical region (265A (“narrow projecting gouge region”); [0024]) and a contact region (265 (main trapezoidal region); [0024]), the vertical region extending vertically and having a first width, and the contact region on the vertical region and having a second width, wider than the first width.
Regarding claim 15, Li shows the vertical region has a side surface inclined to decrease in width toward the source/drain region, and the contact region has a shape expanding from the vertical region (Fig. 1A).
Regarding claim 16, Li shows an upper end of the backside contact plug is above a lower end of the source/drain region (Fig. 1A).
Regarding claim 17, Li shows a lower end of the contact region is below a lower end of the source/drain region (Fig. 1A).
Regarding claim 19, Li discloses in Fig. 1A and related text a semiconductor device (a field effect transistor (FET); [0047]) comprising:
a gate structure (243; [0061]) extending in one direction (vertical direction);
a source/drain region (239 (the one on the right); [0047]) outside of the gate structure; and
a backside contact plug (265, 265A; [0024] and [0059]) below the source/drain region and connected to the source/drain region, wherein,
the backside contact plug includes a vertical region (265A (“narrow projecting gouge region”); [0024]) and a contact region (265 (main trapezoidal region); [0024]), the vertical region extending vertically and having a first width, and the contact region on the vertical region and having a second width, wider than the first width, and
a second central axis of the vertical region (the vertical dashed line on the right) is offset in a horizontal direction from a first central axis of the contact region (the vertical dashed line on the left).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 6-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of US 2024/0030136 A1 (hereinafter “Chang”).
Regarding claim 1, Li discloses in Fig. 1A and related text a semiconductor device (a field effect transistor (FET); [0047]) comprising:
a substrate insulating layer (255; [0024]);
a gate structure (243; [0061]) extending in one direction (vertical direction) on the substrate insulating layer;
a source/drain region (239 (the one on the right); [0047]) outside of the gate structure; and
a backside contact plug (265, 265A; [0024] and [0059]) below the source/drain region and having a second central axis (the vertical dashed line on the left) offset in a horizontal direction from a first central axis of the source/drain region (the vertical dashed line on the right), and connected to the source/drain region.
Li does not disclose the source/drain region includes a first epitaxial layer and a second epitaxial layer, the first epitaxial layer including a first non-silicon element at a first concentration, and the second epitaxial layer on the first epitaxial layer and including a second non-silicon element at a second concentration, greater than the first concentration, and at least a portion of an upper surface of the backside contact plug is in contact with the second epitaxial layer.
Chang teaches in Fig. 27 (viewed upside down) and related text the source/drain region (146; [0034]) includes a first epitaxial layer (146b; [0036]) and a second epitaxial layer (146c; [0037]), the first epitaxial layer including a first non-silicon element (boron) at a first concentration (1E20-8E20 atoms/cm3) ([0036]), and the second epitaxial layer on the first epitaxial layer and including a second non-silicon element (boron) at a second concentration (8E20-3E21 atoms/cm3) ([0037]), greater than the first concentration, and
at least a portion of an upper surface of the backside contact plug (193, 194, 196; [0063] and [0066]) is in contact with the second epitaxial layer.
Li and Chang are analogous art because they both are directed to gate-all-around field effect transistors with backside source/drain contacts and one of ordinary skill in the art would have had a reasonable expectation of success to modify Li with the specified features of Chang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the source/drain region to include a first epitaxial layer and a second epitaxial layer, the first epitaxial layer including a first non-silicon element at a first concentration, and the second epitaxial layer on the first epitaxial layer and including a second non-silicon element at a second concentration, greater than the first concentration, wherein at least a portion of an upper surface of the backside contact plug is in contact with the second epitaxial layer, as taught by Chang, in order to use the first epitaxial layer as a leakage barrier layer to prevent possible diffusion of subsequent backside metallic elements into the gate area (Chang: [0036]), and in order to use the highly doped second epitaxial layer to reduce contact resistance for the source/drain region (Chang: [0037]).
Regarding claim 2, Li in view of Chang disclose the semiconductor device of claim 1.
Li does not disclose the backside contact plug passes through the first epitaxial layer in a lower portion of the source/drain region and is in contact with the first epitaxial layer.
Chang teaches in Fig. 27 (viewed upside down) and related text the backside contact plug (193, 194, 196; [0063] and [0066]) passes through the first epitaxial layer (146b; [0036]) in a lower portion of the source/drain region (146; [0034]) and is in contact with the first epitaxial layer.
Li and Chang are analogous art because they both are directed to gate-all-around field effect transistors with backside source/drain contacts and one of ordinary skill in the art would have had a reasonable expectation of success to modify Li in view of Chang with the specified features of Chang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the backside contact plug to pass through the first epitaxial layer in a lower portion of the source/drain region and to be in contact with the first epitaxial layer, as taught by Chang, in order to electrically connect the backside contact plug to the source/drain region.
Regarding claim 3, Li in view of Chang disclose the backside contact plug comprises a vertical region (Li: 265A (“narrow projecting gouge region”); Fig. 1A; [0024]) extending vertically and having a first width, and a contact region (Li: 265 (main trapezoidal region); Fig. 1A; [0024]) on the vertical region and having a second width, wider than the first width.
Regarding claim 4, Li in view of Chang disclose a third central axis of the vertical region (the vertical dashed line on the right in Fig. 1A of Li) is offset from a fourth central axis of the contact region (the vertical dashed line on the left in Fig. 1A of Li) in the horizontal direction.
Regarding claim 6, Li in view of Chang disclose the semiconductor device of claim 3.
Li does not disclose the vertical region passes through the first epitaxial layer, and at least a portion of a surface of the vertical region is in contact with the first epitaxial layer.
Chang teaches in Fig. 27 (viewed upside down) and related text the vertical region (193, 194, 196; [0063] and [0066]) passes through the first epitaxial layer (146b; [0036]), and at least a portion (193; [0063]) of a surface of the vertical region is in contact with the first epitaxial layer.
Li and Chang are analogous art because they both are directed to gate-all-around field effect transistors with backside source/drain contacts and one of ordinary skill in the art would have had a reasonable expectation of success to modify Li in view of Chang with the specified features of Chang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the vertical region to pass through the first epitaxial layer, wherein at least a portion of a surface of the vertical region is in contact with the first epitaxial layer, as taught by Chang, in order to electrically connect the backside contact plug to the source/drain region.
Regarding claim 7, Li in view of Chang disclose the semiconductor device of claim 1.
Li does not disclose the backside contact plug comprises a metal-semiconductor compound layer corresponding to the upper surface of the backside contact plug.
Chang teaches in Fig. 27 (viewed upside down) and related text the backside contact plug (193, 194, 196; [0063] and [0066]) comprises a metal-semiconductor compound layer (193; [0063]) corresponding to the upper surface of the backside contact plug.
Li and Chang are analogous art because they both are directed to gate-all-around field effect transistors with backside source/drain contacts and one of ordinary skill in the art would have had a reasonable expectation of success to modify Li in view of Chang with the specified features of Chang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the backside contact plug to comprise a metal-semiconductor compound layer corresponding to the upper surface of the backside contact plug, as taught by Chang, in order to reduce a contact resistance between the backside contact plug and the source/drain region.
Regarding claim 8, Li in view of Chang disclose the semiconductor device of claim 1.
Li in view of Chang do not explicitly disclose a horizontal distance between the first central axis and the second central axis ranges from about 0.5 nm to about 20 nm.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a horizontal distance between the first central axis and the second central axis to range from about 0.5 nm to about 20 nm because of nanometer-scale feature sizes in state of the art gate-all-around field effect transistors.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1980). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Regarding claim 9, Li in view of Chang disclose the semiconductor device of claim 1.
Li does not disclose at least one of the first non-silicon element or the second non-silicon element is independently at least one of germanium (Ge) or a doping element.
Chang teaches at least one of the first non-silicon element or the second non-silicon element is independently at least one of germanium (Ge) or a doping element (e.g., boron; [0036]-[0037]).
Li and Chang are analogous art because they both are directed to gate-all-around field effect transistors with backside source/drain contacts and one of ordinary skill in the art would have had a reasonable expectation of success to modify Li in view of Chang with the specified features of Chang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form at least one of the first non-silicon element or the second non-silicon element to be independently at least one of germanium (Ge) or a doping element, as taught by Chang, in order to ensure sufficient electrical conductivity of the source/drain region.
Regarding claim 10, Li in view of Chang disclose an additional source/drain region (Li: 239 (the one on the left); Fig. 1A; [0047]) spaced apart from the source/drain region and not having a contact plug disposed therebelow,
wherein the additional source/drain region further includes a sacrificial epitaxial layer (Li: 237; Fig. 1A; [0024] and [0033]) in a lower portion of the additional source/drain region.
Regarding claim 11, Li in view of Chang disclose the semiconductor device of claim 10, wherein the sacrificial epitaxial layer comprises a third non-silicon element (a dopant; Li: [0033]) in a third concentration.
Li in view of Chang do not disclose the third concentration is greater than the first concentration and the second concentration.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the third concentration to be greater than the first concentration and the second concentration because: “The skilled artisan will be familiar with techniques for epitaxially growing silicon on SiGe30, and will be familiar with techniques for doping silicon” (Li: [0033]).
Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. MPEP 2144.05(II)(A).
Regarding claim 12, Li in view of Chang disclose a backside power structure (Li: 267; Fig. 1A; [0001]-[0002] and [0045]) below the backside contact plug, connected to the backside contact plug, and configured to apply power to the source/drain region.
Regarding claim 13, Li in view of Chang disclose a plurality of channel layers (Li: 209, 213, 217; Fig. 1A; [0047] and [0061]) on the substrate insulating layer, spaced apart from each other in a vertical direction, and surrounded by the gate structure.
Allowable Subject Matter
Claims 5, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, individually or in combination, does not teach or suggest “at least a portion of a surface of the contact region is in contact with the first epitaxial layer” as recited in claim 5, “a lower end of the contact region is above a lower end of the source/drain region” as recited in claim 18, and “a third central axis of the source/drain region is offset in the horizontal direction from the second central axis of the vertical region” as recited in claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT).
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/PETER M ALBRECHT/Primary Examiner, Art Unit 2811