DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of Species I directed to Fig. 4A (claims 1-7 and 9-15) in the reply filed on June 19th, 2026 is acknowledged.
Claim Objections
Claim 1 and 9 are objected to because of the following informalities:
Claim 1 recites “the contact plugs” in lines 9 and 10 which referring back to “a plurality of contact plugs” in line 6 and should be amended to “the plurality of contact plugs” for avoiding confusion.
Claim 9 recites “among the plurality of contact plugs:” in lines 1-2 which contains a colon symbol and should be removed for avoiding confusion.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-7, 9-12, and 14-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by KATO et al. (Pub. No.: US 2023/0262973 A1), hereinafter as KATO.
Regarding claim 1, KATO discloses a memory device in Figs. 3-5 comprising: a stack structure (stack structure of insulating layer 23 and conductive layers 24-26) including a plurality of conductive layers (a plurality of conductive layers 25, conductive layer 24 and conductive layer 26) and a plurality of interlayer insulating layers (plurality of insulating layer 23), which are alternately stacked along a first direction (Z direction) (see Fig. 4 and [0081-0083]), the stack structure including a cell region (memory array area MA) and a contact region (Hook-up area HA), the contact region extending from the cell region and having a stepped structure (staircase structure) (see Figs. 3-4 and [0064], [0073]); a plurality of contact plugs (a plurality of contact plugs CP) respectively in contact with the plurality of conductive layers in the contact region, the plurality of contact plugs extending in the first direction (see Figs. 4-5 and [0072], [0086-0087]); and a plurality of lower pillars (a plurality of insulating plug 30) respectively in contact with the contact plugs, the plurality of lower pillars being located on the bottom of the contact plugs in the stack structure (see Figs. 3-5 and [0079], [0083-0084]), wherein each of the plurality of lower pillars includes: a liner layer (insulating layer 32) in contact with the stack structure (insulating layer 32 contacts at least one of conductive layers 24, 25, 26 and/or insulating layer 23) (see Figs. 4-5 and [0085], [0091]); and a pillar structure (insulating layer 31) surrounded by the liner layer (see Figs. 4-5 and [0085]).
Regarding claim 2, KATO discloses the memory device of claim 1, wherein each of the plurality of lower pillars (insulating plug 30) are respectively located in a plurality of openings (plurality of openings 30A) penetrating the stack structure (see Figs. 4, 14), and wherein each of the plurality of openings penetrates the plurality of conductive layers with a first width (a width of the lower portion of opening 30A) and penetrates the plurality of interlayer insulating layers with a second width (a width of the upper portion of opening 30A) that is greater than the first width (opening 30A has tapered shape) (see Figs. 4-14 and [0116-0118]).
PNG
media_image1.png
688
622
media_image1.png
Greyscale
Regarding claim 3, KATO discloses the memory device of claim 2, wherein at least a portion of each of the plurality of contact plugs (first portion of contact plug CC) has a third width (a width measured at cross section B1) that is greater than the second width (greater than the width of the upper portion of opening 30A because the opening 30A has tapered shape) (see annotated Fig. 5 above, Figs. 14, 29-31 and [0089-0090]).
Regarding claim 4, KATO discloses the memory device of claim 2, wherein the liner layer (insulating layer 32) is formed along an inner wall of each of the plurality of openings (see Figs. 4, 14, 19 and [0118]).
Regarding claim 6, KATO discloses the memory device of claim 1, wherein the pillar structure is spaced apart from the stack structure through the liner layer (see Fig. 4-5).
Regarding claim 7, KATO discloses the memory device of claim 1, wherein a top surface of the pillar structure is in contact with a bottom surface of a respective contact plug, among the plurality of contact plugs (see Figs. 4-5).
Regarding claim 9, KATO discloses the memory device of claim 1, wherein a first contact plug (first contact plug CC, starting from the right of Fig. 4), among the plurality of contact plugs: is electrically connected to a first conductive layer (conductive layer 26 being the select gate line SGD), among the plurality of conductive layers (see Fig. 4 and [0074], [0123]); and is in contact with a first lower pillar (first insulating plug 30 being tallest one, starting from the right of Fig. 4), among the plurality of lower pillars.
Regarding claim 10, KATO discloses the memory device of claim 9, wherein the first contact plug includes: an extension part (second portion of contact plug CC above conductive line 26 but excluding the exposed portion of the contact plug CC above insulating layer 28) extending in the first direction (see Fig. 4); and a protrusion part (protruding part of the first portion of contact plug CC below conductive layer 26) protruding toward the first lower pillar from the extension part (see Figs. 4-5 and [0089]).
Regarding claim 11, KATO discloses the memory device of claim 10, wherein the extension part of the first contact plug is in contact with a top surface of the first conductive layer (electrically contacts the top surface of conductive layer 26) (see Fig. 4-5).
Regarding claim 12, KATO discloses the memory device of claim 10, wherein the protrusion part of the first contact plug is in contact with an inner wall of the first conductive layer exposed by an opening (opening 30A) and a top surface of the first lower pillar (electrically contacts inner wall of conductive layer 26 and physically contacts a top surface of insulating layer 30) (see Figs. 4-5, 18).
Regarding claim 14, KATO discloses the memory device of claim 10, further comprising an upper insulating layer (insulating layer 28) covering the stack structure, wherein the extension part of the first contact plug is located inside the upper insulating layer (the extension part of contact plug CC can be interpreted for being within the insulating layer 28) (see Figs. 4-5 and [0081]).
Regarding claim 15, KATO discloses the memory device of claim 10, wherein the plurality of conductive layers further include a second conductive layer (conductive layer 25 being world line WL7) located below the first conductive layer, and wherein the first lower pillar penetrates the second conductive layer (see Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-7, and 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Cui (Patent No.: US 9,853,038 B1) and further in view of by KATO et al. (Pub. No.: US 2023/0262973 A1), hereinafter as KATO.
Regarding claim 1, Cui discloses a memory device in Figs. 25A-25B comprising: a stack structure including a plurality of conductive layers (plurality of conductive layers 46) and a plurality of interlayer insulating layers (plurality of insulating layers 32) (see Fig. 25A, column 7, lines 16-20 and column 22, lines 54-64), which are alternately stacked along a first direction (vertical direction in Fig. 25A), the stack structure including a cell region (memory array region 100) and a contact region (contact region 300), the contact region extending from the cell region and having a stepped structure (see Fig. 25A, column 6, lines 27-36); a plurality of contact plugs (plurality of contact via structures 86) respectively in contact with the plurality of conductive layers in the contact region (see Fig. 25A, column 27 and lines 12-26), the plurality of contact plugs extending in the first direction (see Fig. 25A); and a plurality of lower pillars (a plurality of pillars 24B ) respectively in contact with the contact plugs, the plurality of lower pillars being located on the bottom of the contact plugs in the stack structure (see Fig. 25A, column 26, lines 3-14, column 27 and lines 20-35); wherein each of the plurality of lower pillars comprising a pillar structure (each of the plurality of pillars 24B being the pillar structure) (see Fig. 25A).
Cui fails to disclose wherein each of the plurality of lower pillars includes: a liner layer in contact with the stack structure for making the pillar structure surrounded by the liner layer.
KATO discloses a memory device in Figs. 3-5 comprises a plurality of contact plugs (a plurality of contact plugs CP) respectively in contact with the plurality of conductive layers in the contact region, the plurality of contact plugs extending in the first direction (see Figs. 4-5 and [0072], [0086-0087]); a plurality of lower pillars (a plurality of insulating plug 30) respectively in contact with the contact plugs, the plurality of lower pillars being located on the bottom of the contact plugs in the stack structure (see Figs. 3-5 and [0079], [0083-0084]), wherein each of the plurality of lower pillars includes: a liner layer (insulating layer 32) in contact with the stack structure (insulating layer 32 contacts at least one of conductive layers 24, 25, 26 and/or insulating layer 23) (see Figs. 4-5 and [0085], [0091]); and a pillar structure (insulating layer 31) surrounded by the liner layer (see Figs. 4-5 and [0085]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the liner layer of KATO (insulating layer 32) into the plurality of lower pillars of Cui (plurality of insulating plug 30) for contacting the stack structure and surrounding each of the plurality of the pillar structures because the modified structure would giving a benefit for preventing the conductive layers as word line being short circuited and further preventing metal diffusion from the conductive layers into nearby structures.
Regarding claim 2, the combination of Cui and KATO discloses the memory device of claim 1, wherein each of the plurality of lower pillars are respectively located in a plurality of openings (plurality of openings 39) penetrating the stack structure (see Figs. 9, 25A), and wherein each of the plurality of openings penetrates the plurality of conductive layers with a first width (a width of opening portion within conductive layers 46) and penetrates the plurality of interlayer insulating layers with a second width (a width of the opening portion within insulating layer 32) that is greater than the first width (see Figs. 9, 25A and column 12, lines 59 though column 11, lines 19).
Regarding claim 4, the combination of Cui and KATO discloses the memory device of claim 2, wherein the liner layer (insulating layer 32) is formed along an inner wall of each of the plurality of openings (see KATO and Figs. 4, 14, 19 and [0118]).
Regarding claim 5, the combination of Cui and KATO discloses the memory device of claim 1, wherein the pillar structure (pillar 24B) includes: a vertical part (vertical portion of pillar 24B within conductive layer 46) extending in the first direction (see Cui and Fig. 25A); and a horizontal protrusion part (horizontal portion of pillar 24B within insulating layer 32) protruding toward each of the plurality of interlayer insulating layers from the vertical part (see Cui and Fig. 25A).
Regarding claim 6, the combination of Cui and KATO discloses the memory device of claim 1, wherein the pillar structure is spaced apart from the stack structure through the liner layer (see Cui, Fig. 25A and KATO, Figs. 4-5).
Regarding claim 7, the combination of Cui and KATO discloses the memory device of claim 1, wherein a top surface of the pillar structure is in contact with a bottom surface of a respective contact plug, among the plurality of contact plugs (see Cui and Fig. 25A).
Regarding claim 9, the combination of Cui and KATO discloses the memory device of claim 1, wherein a first contact plug (contact via structure 86 starting from the right of Fig. 25A of Cui), among the plurality of contact plugs: is electrically connected to a first conductive layer (the topmost conductive layer 46), among the plurality of conductive layers (see Cui, Fig. 25A]); and is in contact with a first lower pillar (first pillar 24B being tallest one, starting from the right of Fig. 25A of Cui), among the plurality of lower pillars.
Regarding claim 10, the combination of Cui and KATO discloses the memory device of claim 9, wherein the first contact plug includes: an extension part (upper portion of contact via structure 86 above the topmost conductive layer 46) extending in the first direction (see Fig. 25A of Cui); and a protrusion part (protruding part of the lower portion of pillar 24B within the topmost conductive layer 46) protruding toward the first lower pillar from the extension part (see Fig. 25A of Cui).
Regarding claim 11, the combination of Cui and KATO discloses the memory device of claim 10, wherein the extension part of the first contact plug is in contact with a top surface of the first conductive layer (see Fig. 25A of Cui).
Regarding claim 12, the combination of Cui and KATO discloses the memory device of claim 10, wherein the protrusion part of the first contact plug is in contact with an inner wall of the first conductive layer exposed by an opening (opening 39) and a top surface of the first lower pillar (top surface of pillar 24B) (see Cui and Figs. 9, 25A).
Regarding claim 13, the combination of Cui and KATO discloses the memory device of claim 10, wherein a boundary surface between the protrusion part of the first contact plug and the first lower pillar is located between a top surface and a bottom surface of the first conductive layer (the boundary surface between the protrusion part of the lower portion of contact via structure 86 and pillar 24B between the top surface and the bottom surface of conductive layer 46) (see Fig. 25A of Cui).
Regarding claim 14, the combination of Cui and KATO discloses the memory device of claim 10, further comprising an upper insulating layer (dielectric layer 73) covering the stack structure, wherein the extension part of the first contact plug is located inside the upper insulating layer (see Cui, Fig. 25A and column 19, lines 48-52).
Regarding claim 15, the combination of Cui and KATO discloses the memory device of claim 10, wherein the plurality of conductive layers further include a second conductive layer (the second topmost conductive layer 46) located below the first conductive layer, and wherein the first lower pillar (pillar 24B) penetrates the second conductive layer (see Fig. 25A of Cui).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
Prosecution Insights