DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “bonding a third semiconductor substrate onto a fourth semiconductor substrate based on the first displacement data to reduce an overlay change between the third and fourth semiconductor substrates, wherein the third and fourth semiconductor substrates comprise semiconductor substrates of a same type as the first and second semiconductor substrates” of claims 2 and 12, and the “and bonding a plurality of different semiconductor substrates to each other based on the first displacement data” of claim 20 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Iga (US Pub. No. 2024/0120215) in view of Haensch (US Patent No. 8,247,895).
Regarding claim 1, in FIGs. 1-12, Iga discloses a method of manufacturing a semiconductor device, the method comprising: bonding a first semiconductor substrate (10-1) on a second semiconductor substrate (10-2; paragraph [0030]); performing a first physical parameter measurement (paragraph [0074]) on a first surface (14) of the first semiconductor substrate to obtain first displacement data (determine if excessive region has been removed); polishing the first surface of the first semiconductor substrate after the first displacement data is obtained (in the case where the if excessive region is still present, more polishing/grinding is required); performing a second physical parameter measurement on the polished first surface of the first semiconductor substrate to obtain second displacement data (determine if excessive region has been removed); performing a subsequent polishing step (paragraph [0074]).
Iga appears not to explicitly disclose forming circuit patterns on the polished first surface of the first semiconductor substrate based on the second displacement data.
However, Haensch discloses a similar process wherein after polishing a wafer, I/O, BEOL fan-out, and solder bumps are formed to provide external connection to the semiconductor devices on a wafer (col. 21, lines 42-50).
To provide external connection to the semiconductor devices on the wafers (or “substrates”) it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form I/O, and/or BEOL fan-out, and/or solder bumps after polishing (e.g. based on the second displacement data because the process will not proceed to the subsequent polishing step until the excessive region has been removed).
Regarding claim 3, the combination of Iga and Haensch discloses (see Iga, FIG. 2) that bonding the first semiconductor substrate comprises: bonding the first semiconductor substrate such that a second surface (13) of the first semiconductor substrate opposite to the first surface (14) faces the second semiconductor substrate (10-2), a plurality of circuit elements (18) and redistribution wires (paragraph [0033]) electrically connected to the circuit elements being formed on the second surface, and wherein the forming the circuit patterns comprises, forming the circuit patterns such that the circuit patterns are overlaid with the circuit elements or the redistribution wires based on the second displacement data (e.g. based on the second displacement data because the process will not proceed to the subsequent polishing step until the excessive region has been removed).
Regarding claim 4, the combination of Iga and Haensch discloses (see Iga, FIG. 2) that the forming the circuit patterns further comprises forming through silicon vias that are electrically connected to the circuit elements or the redistribution wires (paragraph [0033]).
Regarding claim 5, the combination of Iga and Haensch discloses (see Iga, FIG. 2) that the circuit patterns comprise power supply patterns that are configured to supply power to the circuit elements (at least some of the circuit patterns are required to be power supply patterns to provide power to the plurality of circuit elements).
Allowable Subject Matter
Claims 2 and 6-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior art failed to disclose or reasonably suggest the claimed method particularly characterized by bonding a third semiconductor substrate onto a fourth semiconductor substrate based on the first displacement data to reduce an overlay change between the third and fourth semiconductor substrates.
Regarding claims 6-8, the prior art failed to disclose or reasonably suggest the claimed method particularly characterized by the first and second physical parameter measurements comprising a nanoindentation measurement that is able to obtain the first and second displacement data, respectively, from the first surface using a plurality of probes spaced apart by a predetermined distance.
Regarding claim 9, the prior art failed to disclose or reasonably suggest the claimed method particularly characterized by the first and second physical parameter measurements obtain the first and second displacement data, respectively, by measuring residual stresses on the first surface.
Regarding claim 10, the prior art failed to disclose or reasonably suggest the claimed method particularly characterized by the polishing the first surface comprises removing a first change in a displacement that is applied on the first surface in a process of obtaining the first displacement data, and wherein the forming the circuit patterns comprises reflecting a second change in a displacement that is applied on the polished first surface in a process of obtaining the second displacement data to form the circuit patterns.
Claims 11-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 11-19, the prior art failed to disclose or reasonably suggest the claimed method particularly characterized by performing a first physical parameter measurement on a first surface of the first semiconductor substrate to obtain first displacement data, the first displacement data indicating a residual stress of the first surface; performing a second physical parameter measurement on the polished first surface of the first semiconductor substrate to obtain second displacement data, the second displacement data indicating residual stress of the polished first surface
Regarding claim 20, the prior art failed to disclose or reasonably suggest the claimed method particularly characterized by obtaining first displacement data indicating a residual stress of a surface from any one surface selected from among the semiconductor substrates through a physical parameter measurement; polishing the surface of the semiconductor substrate such that a displacement change applied on the surface in a process of obtaining the first displacement data is removed; obtaining second displacement data indicating a residual stress of the polished surface from the polished surface of the semiconductor substrate through the physical parameter measurement; and bonding a plurality of different semiconductor substrates to each other based on the first displacement data.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891
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