DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura USPG Pub. No.: US 2013/0087788 in view of itself in a single reference rejection, and, alternatively, in view of Matsui et al. USPG Pub. No.: US 2004/0257847.
Regarding Claim 1, Nakamura teaches an apparatus, comprising:
a plurality of dies arranged in a stack (see [0046] and figure 1, integrated circuit layers 10 and 20);
wherein:
each of the plurality of dies comprise a plurality of metallization layers (see [0130], which discusses the use of metallization layers as connection terminals rather than adhesive; see [0059] which describes the implementation of said metal layers into the apparatus seen in figure 1); and
at least two of the plurality of memory dies comprise an area devoid of their respective plurality of metallization layers and the portion of each of the at least two of the plurality of memory dies are physically in line and perpendicular to an outside surface of the stack (see figure 1 and [0050] stating that 23c are light-transmitting regions, preferably free from wiring in order to allow the passage of light to and from rectifying diodes 15 and 25, in order to probe the stacked device).
A person of ordinary skill having the benefit of Nakamura can readily apply the teachings to any type of semiconductor device (see Nakamura [0004] which alludes to test methods of memory die stacks using empty spaces for probing being well known). However, alternatively, Matsui discloses an IC chip stack that is specifically a memory die stack for use with a test circuit in which the plurality of memory dies each includes a group of memory cells (see Matsui [0057]-[0058], [0099]-[0100], [0145], and figures 1, 5, and 9 teaching a stack of memory dies, each with an array of memory cells, having a space devoid of interference for use with a test device). It would have been obvious to one of ordinary skill in the art at the time of filing to have tested stacked memory dies, such as those taught in Matsui, as they are a subclass of IC chips, and structurally similar to any other die stack that would benefit from such testing, such as the generically described die stacks seen in figure 1 of Nakamura (also see Matsui figures 1-2, and see Nakamura [0011], in which any stack of IC chips should be tested to ensure that there is not a failure point).
Regarding Claim 2, Nakamura, or Nakamura and Matsui, teach the apparatus of claim 1, wherein a circuit is positioned opposite the outside surface of the stack and the devoid area of the at least two of the plurality of memory dies are between the circuit and the outside surface (see Nakamura [0121]-[0122] and figure 13, camera 101, which is facing opposite to chip 1A, particularly the portion of the camera sensor that is positioned opposite the devoid area, which is seen more clearly in figure 1).
Regarding Claim 3, Nakamura, or Nakamura and Matsui, teach the apparatus of claim 2, wherein a distance between the circuit and the outside surface is correlated with a particular size lens (see Nakumura figure 13, the size of lens 109 determines a distance between the circuit and outside surface).
Regarding Claim 4, Nakamura, or Nakamura and Matsui, teach the apparatus of claim 3, wherein the particular size lens is configured to focus a light source onto the circuit (see figure 13 and [0121]-[0122]).
Regarding Claim 5, Nakamura, or Nakamura and Matsui, teach the apparatus of claim 4, wherein the light source is a high intensity light (HIL) source (see [0121]-[0126] in which a laser can be considered a high intensity light source).
Regarding Claim 6, Nakamura, or Nakamura and Matsui, teach the apparatus of claim 3, wherein the particular size lens is a solid immersion lens (SIL) (see [0121]-[0122] discussing lens that are interpreted as solid immersion lenses under the broadest reasonable interpretation of the terminology).
Regarding Claim 7, Nakamura teaches an apparatus, comprising:
a plurality of memory dies arranged in a stack (see [0046] and figure 1, integrated circuit layers 10 and 20);
wherein:
each of the plurality of memory dies comprise a plurality of metallization layers (see [0130], which discusses the use of metallization layers as connection terminals rather than adhesive; see [0059] which describes the implementation of said metal layers into the apparatus seen in figure 1); and
a plurality of diodes are coupled to the plurality of metallization layers (see figures 1, 2, and 4 as well as [0130], which discusses the use of metallization layers as connection terminals rather than adhesive; see [0059] which describes the implementation of said metal layers into the apparatus seen in figure 1); and
a first diode of the plurality of diodes is coupled via at least one of the plurality of metallization layers to a second diode of the plurality of diodes such that the second diode is a particular distance from any of the plurality of diodes (see figures 1 and 4 as well as [0054]-[0055], which discloses the first and second diodes and their coupling to metallization layers. These sets of diodes 25 and 15 can be seen at specified distances in figure 1).
A person of ordinary skill having the benefit of Nakamura can readily apply the teachings to any type of semiconductor device (see Nakamura [0004] which alludes to test methods of memory die stacks using empty spaces for probing being well known). However, alternatively, Matsui discloses an IC chip stack that is specifically a memory die stack for use with a test circuit in which the plurality of memory dies each includes a group of memory cells (see Matsui [0057]-[0058], [0099]-[0100], [0145], and figures 1, 5, and 9 teaching a stack of memory dies, each with an array of memory cells, having a space devoid of interference for use with a test device). It would have been obvious to one of ordinary skill in the art at the time of filing to have tested stacked memory dies, such as those taught in Matsui, as they are a subclass of IC chips, and structurally similar to any other die stack that would benefit from such testing, such as the generically described die stacks seen in figure 1 of Nakamura (also see Matsui figures 1-2, and see Nakamura [0011], in which any stack of IC chips should be tested to ensure that there is not a failure point).
Regarding Claim 8, Nakamura, or Nakamura and Matsui, teach the apparatus of claim 7, wherein the second diode is configurable to be deactivated while the first diode is enabled (seen in Nakamura figures 1 and 4 in which the circuit demonstrates such a configuration).
Regarding Claim 9, Nakamura, or Nakamura and Matsui, teach the apparatus of claim 7, wherein a first signal transferred through the first diode occurs simultaneous with a second signal transferred through the second diode (seen in Nakamura figures 1 and 4 in which the circuit demonstrates such a configuration).
Regarding Claim 10, Nakamura, or Nakamura and Matsui, teach the apparatus of claim 7, wherein the particular distance is greater than 200 nanometers (see Nakamura [0071]-[0072] in which a plurality of diodes can be stacked, not limited to the three dies seen in figure 9. Thus under the broadest reasonable interpretation of the claimed language, a scenario exists where the diodes of two dies that are stacked far enough apart exceed a 200nm distance, thus meeting the claimed language).
Conclusion
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/MICHAEL A HARRISON/Examiner, Art Unit 2852