DETAILED ACTION
This action is in response to the Application filed on 12/11/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/09/2014 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim(s) 6 is/are objected to because of the following informalities:
Claim(s) 6 recite(s) “an dan inductor”. It appears that it should be “an inductor”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 6 and 11 recite “M-level converter cell”. However, M is not defined in the claim and the metes and bounds are not defined which renders the claims indefinite. For examination purpose the examiner is going to assume that M is equal or higher than 2, since Fig. 3A-3B and 6A – 6B corresponds to a two level converter.
Claims 2 – 5 and 7 – 8 and 12 – 15 depends directly or indirectly from a rejected claim and are therefore also rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claims 1 – 2, 6 – 7 and 11 – 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2022/0045622; (hereinafter Oi) in view of US Pub. No. 2023/0283198; (hereinafter Kong).
Regarding claim 1, Oi [e.g. Fig. 3] discloses a method of pre-charging at least one capacitor [e.g. FC] coupled to an M-level converter cell that includes a node, a plurality of high-side power transistors [e.g. T1-T2] coupled in series to the node, a plurality of low-side power transistors [e.g. T3-T4] coupled in series to the node, and an inductor [e.g. L] coupled to the node, wherein the M-level converter cell is configured to be connected to the at least one capacitor between a first pair of power transistors of the plurality of high-side power transistors and a second pair of power transistors of the plurality of low-side power transistors, the method including: (a) setting an outermost low-side power transistor [e.g. T4] to a current-limiting reduced gate drive mode [e.g. Fig. 3(a); OFF]; (b) setting all of the plurality of high-side power transistors to an OFF state [e.g. Fig. 3c]; (c) setting all of the plurality of low-side power transistors, except the innermost low-side power transistor [e.g. T3] closest to the node, to an ON state [e.g. Fig. 3(d)]; (d) toggling the innermost low-side power transistor to commence charging all of the at least one capacitor [e.g. Fig. 3(a)-Fig. 3(b), Fig. 3(d)], and continuing toggling until a capacitor [e.g. FC] associated with the innermost low-side power transistor is fully pre-charged to a respective target voltage level [e.g. paragraphs 071 – 073 recite “FIG. 3 shows an electric current path by each switching pattern. When both the flying capacitor FC and the lower voltage side filter capacitor C2 are to be charged, the first semiconductor switching element T1 is turned on at S5 so that an electric current flows along a path shown in FIG. 3 (b) (C1->T1->FC->T3->L->C2) to charge the flying capacitor FC and the lower voltage side filter capacitor C2. However, when both the flying capacitor FC and the lower voltage side filter capacitor C2 are already charged to some extent and Vfc+Vb≥Va is satisfied, no electric current flows even with only the first semiconductor switching element T1 turned on. In this situation, at S6, the second semiconductor switching element T2 is also turned on so that an electric current flows along a path shown in FIG. 3 (a) (C1->T1->T2->L->C2), and at S5, only the second semiconductor switching element T2 is turned off to cause an electric current to flow along the path shown in FIG. 3 (b). When the lower voltage side filter capacitor voltage Vb is sufficient and only the flying capacitor FC is to be charged, and Vb>Vfc is satisfied, the fourth semiconductor switching element T4 is turned on at S8 so that an electric current flows along a path shown in FIG. 3 (d) (C2->L->T2->FC->T4) to charge the flying capacitor FC from the lower voltage side filter capacitor C2”]; (e) if any remaining capacitors need to be fully pre-charged, then toggling a next low-side power transistor, further from the node, along with all previously toggling low-side power transistors until a capacitor associated with such next low-side power transistor is fully pre-charged, and repeating this step until all capacitors of the at least one capacitor are fully pre-charged to respective target voltage levels [e.g. (e) is not required since there’s no additional capacitor of the at least one capacitor and no next low-side power FET since the claim only requires a minimum of two low side transistors].
Oi fails to disclose where the transistors are FET; the inductor coupled configured to be coupled to a battery.
Kong [e.g. Fig. 2] teaches where the transistors are FET [e.g. S1-S4, see MSOFET symbols]; the inductor [e.g. L] configured to be coupled to a battery [e.g. Vbat].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Oi by where the transistors are FET; the inductor configured to be coupled to a battery as taught by Kong in order of being able to charge a battery load with enhanced switching performance, paragraph 032.
Regarding claim 2, Oi [e.g. Fig. 3] discloses, wherein pre-charging of each of the at least one capacitor is through an inherent body diode of a respective high-side power transistor [e.g. diode of T2 at Fig. 3(d), see diode polarity current from anode to cathode; paragraph 073 above in claim 1].
Oi fails to disclose where the high-side power transistors are FET.
Kong [e.g. Fig. 2] teaches where the high-side power transistors are FET [e.g. S1-S4, see MSOFET symbols].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Oi by where the high-side power transistors are FET as taught by Kong in order of being able to provide better switching performance.
Regarding claim 6, Oi [e.g. Fig. 3] discloses a circuit configuration for an M-level converter cell for pre-charging at least one capacitor [e.g. FC] coupled to the M-level converter cell, wherein the M-level converter cell includes a node, a plurality of high-side power transistors [e.g. T1-T2] coupled in series to the node, a plurality of low-side power transistors [e.g. T3-T4] coupled in series to the node, an dan inductor [e.g. L] coupled to the node, wherein the M-level converter cell is configured to be connected to the at least one capacitor between a first pair of power transistors [e.g. T1-T2] of the plurality of high-side power transistors and a second pair of power transistors [e.g. T3-T4] of the plurality of low-side power transistors, the circuit configuration including: (a) an outermost low-side power transistor [e.g. T4] set in a current-limiting reduced gate drive mode [e.g. Fig. 3(a); OFF]; (b) all of the plurality of high-side power transistors set to an OFF state [e.g. Fig. 3c]; (c) all of the plurality of low-side power transistors, except the innermost low-side power transistor [e.g. T3] closest to the node, set to an ON state [e.g. Fig. 3(d)]; (d) the innermost low-side power transistor set to toggling to commence charging all of the at least one capacitor [e.g. Fig. 3(a)-Fig. 3(b), Fig. 3(d)], and to continuing toggling until a capacitor [e.g. FC] associated with the innermost low-side power transistor is fully pre-charged to a respective target voltage level [e.g. paragraphs 071 – 073 recite “FIG. 3 shows an electric current path by each switching pattern. When both the flying capacitor FC and the lower voltage side filter capacitor C2 are to be charged, the first semiconductor switching element T1 is turned on at S5 so that an electric current flows along a path shown in FIG. 3 (b) (C1->T1->FC->T3->L->C2) to charge the flying capacitor FC and the lower voltage side filter capacitor C2. However, when both the flying capacitor FC and the lower voltage side filter capacitor C2 are already charged to some extent and Vfc+Vb≥Va is satisfied, no electric current flows even with only the first semiconductor switching element T1 turned on. In this situation, at S6, the second semiconductor switching element T2 is also turned on so that an electric current flows along a path shown in FIG. 3 (a) (C1->T1->T2->L->C2), and at S5, only the second semiconductor switching element T2 is turned off to cause an electric current to flow along the path shown in FIG. 3 (b). When the lower voltage side filter capacitor voltage Vb is sufficient and only the flying capacitor FC is to be charged, and Vb>Vfc is satisfied, the fourth semiconductor switching element T4 is turned on at S8 so that an electric current flows along a path shown in FIG. 3 (d) (C2->L->T2->FC->T4) to charge the flying capacitor FC from the lower voltage side filter capacitor C2”]; and (e) a next low-side power transistor, further from the node, set to toggling along with all previously toggling low-side power FETs until a capacitor associated with such next low-side power transistor is fully pre-charged to a respective target voltage level [e.g. (e) is not required since there’s no additional capacitor of the at least one capacitor and no next low-side power FET since the claim only requires a minimum of two low side transistors].
Oi fails to disclose where the transistors are FET; the inductor coupled configured to be coupled to a battery.
Kong [e.g. Fig. 2] teaches where the transistors are FET [e.g. S1-S4, see MSOFET symbols]; the inductor [e.g. L] coupled configured to be coupled to a battery [e.g. Vbat].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Oi by where the high-side power transistors are FET as taught by Kong in order of being able to charge a battery load with enhanced switching performance.
Regarding claim 7, Oi [e.g. Fig. 3] discloses wherein each of the at least one capacitor is pre-charged through an inherent body diode of a respective high-side power transistor [e.g. diode of T2 at Fig. 3(d), see diode polarity current from anode to cathode; paragraph 073 above in claim 1].
Oi fails to disclose where the high-side power transistors are FET.
Kong [e.g. Fig. 2] teaches where the high-side power transistors are FET [e.g. S1-S4, see MSOFET symbols].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Oi by where the high-side power transistors are FET as taught by Kong in order of being able to provide enhanced switching performance.
Regarding claim 11, Oi [e.g. Fig. 3] discloses a circuit configuration for an M-level converter cell for pre-charging a capacitor [e.g. FC] coupled to the M-level converter cell, wherein the M-level converter cell includes a node, a plurality of high-side power transistors [e.g. T1-T2] coupled in series to the node, a plurality of low-side power transistors [e.g. T3-T4] coupled in series to the node, and an inductor [e.g. L] coupled to the node, wherein the M-level converter cell is configured to be connected to the capacitor between an innermost pair of power transistors of the plurality of high-side power transistors and innermost pair of power transistors of the plurality of low-side power transistors, the circuit configuration including: (a) an outermost low-side power transistor [e.g. T4] set in a current-limiting reduced gate drive mode [e.g. Fig. 3(a); OFF]; (b) all of the plurality of high-side power transistors set to an OFF state[e.g. Fig. 3c]; (c) all of the plurality of low-side power transistors, except the innermost low-side power transistor [e.g. T3] closest to the node, set to an ON state [e.g. Fig. 3(d)]; and (d) the innermost low-side power transistor set to toggling to commence charging the capacitor [e.g. Fig. 3(a)-Fig. 3(b), Fig. 3(d), and to continuing toggling until the capacitor is fully pre-charged to a respective target voltage level [e.g. paragraphs 071 – 073 recite “FIG. 3 shows an electric current path by each switching pattern. When both the flying capacitor FC and the lower voltage side filter capacitor C2 are to be charged, the first semiconductor switching element T1 is turned on at S5 so that an electric current flows along a path shown in FIG. 3 (b) (C1->T1->FC->T3->L->C2) to charge the flying capacitor FC and the lower voltage side filter capacitor C2. However, when both the flying capacitor FC and the lower voltage side filter capacitor C2 are already charged to some extent and Vfc+Vb≥Va is satisfied, no electric current flows even with only the first semiconductor switching element T1 turned on. In this situation, at S6, the second semiconductor switching element T2 is also turned on so that an electric current flows along a path shown in FIG. 3 (a) (C1->T1->T2->L->C2), and at S5, only the second semiconductor switching element T2 is turned off to cause an electric current to flow along the path shown in FIG. 3 (b). When the lower voltage side filter capacitor voltage Vb is sufficient and only the flying capacitor FC is to be charged, and Vb>Vfc is satisfied, the fourth semiconductor switching element T4 is turned on at S8 so that an electric current flows along a path shown in FIG. 3 (d) (C2->L->T2->FC->T4) to charge the flying capacitor FC from the lower voltage side filter capacitor C2”].
Oi fails to disclose where the transistors are FET; the inductor coupled configured to be coupled to a battery.
Kong [e.g. Fig. 2] teaches where the transistors are FET [e.g. S1-S4, see MSOFET symbols]; the inductor [e.g. L] coupled configured to be coupled to a battery [e.g. Vbat].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Oi by where the transistors are FET; the inductor coupled configured to be coupled to a battery as taught by Kong in order of being able to charge a battery with enhanced switching performance.
Regarding claim 12, Oi [e.g. Fig. 3] discloses wherein the capacitor is pre-charged through an inherent body diode of a respective high-side power transistor [e.g. diode of T2 at Fig. 3(d), see diode polarity current from anode to cathode; paragraph 073 above in claim 1].
Oi fails to disclose where the high-side power transistors are FET.
Kong [e.g. Fig. 2] teaches where the high-side power transistors are FET [e.g. S1-S4, see MSOFET symbols].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Oi by where the high-side power transistors are FET as taught by Kong in order of being able to provide enhanced switching performance.
Claims 3, 5, 8, 10, 13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oi in view of Kong, and further in view of US Pub. No. 2024/0305194; (hereinafter Anderson).
Regarding claim 3, Oi fails to disclose further including sensing current through the inductor and setting any toggling low-side power FETs in an ON state to an OFF state if current through the inductor exceeds a selected level.
Anderson [e.g. Fig. 4] teaches further including sensing current [e.g. 410, 411] through the inductor [e.g. Lr] and setting any toggling low-side power FETs [e.g. lower S2 and S1] in an ON state to an OFF state [e.g. Fig. 6; see inverse of U1 and U2] if current through the inductor exceeds a selected level [e.g. see Fig. 6 with respect to signal inversed U1, U2 at and after time point 604. Paragraph 044 recites “At a second time point 604, the peak of the inductor current has been found by the inductor current matching or exceeding the peak current reference waveform 601”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Oi by further including sensing current through the inductor and setting any toggling low-side power FETs in an ON state to an OFF state if current through the inductor exceeds a selected level as taught by Anderson in order of being able to provide a wider range of duty cycle operations, paragraph 033.
Regarding claim 5, Oi fails to disclose wherein the outermost low-side power FET is controlled by a driver circuit powered by a reduced gate drive circuit configured to selectively set the outer-most low-side power FET to a full gate-drive mode or to a current-limiting reduced gate-drive mode.
Anderson [e.g. Fig. 4] teaches wherein the outermost low-side power FET [e.g. lowest MOSFET directly connected to ground (Inverse of S1)] is controlled by a driver circuit [e.g. 417] powered by a reduced gate drive circuit [e.g. 415] configured to selectively set the outer-most low-side power FET to a full gate-drive mode [e.g. ON] or to a current-limiting reduced gate-drive mode [e.g. OFF].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Oi by wherein the outermost low-side power FET is controlled by a driver circuit powered by a reduced gate drive circuit configured to selectively set the outer-most low-side power FET to a full gate-drive mode or to a current-limiting reduced gate-drive mode as taught by Anderson in order of being able to provide a wider range of duty cycle operations, paragraph 033.
Regarding claim 8, Oi fails to disclose further including a first sensor coupled to the M-level converter cell and configured to toggle any toggling low-side power FETs from an ON state to an OFF state if current through the inductor exceeds a selected level.
Anderson [e.g. Fig. 4] teaches further including a first sensor [e.g. 410, 411] coupled to the M-level converter cell and configured to toggle any toggling low-side power FETs [e.g. lower S2 and S1] from an ON state to an OFF state if current through the inductor exceeds a selected level [e.g. Fig. 6; see inverse of U1 and U2] if current through the inductor exceeds a selected level [e.g. see Fig. 6 with respect to signal inversed U1, U2 at and after time point 604. Paragraph 044 recites “At a second time point 604, the peak of the inductor current has been found by the inductor current matching or exceeding the peak current reference waveform 601”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Oi by further including a first sensor coupled to the M-level converter cell and configured to toggle any toggling low-side power FETs from an ON state to an OFF state if current through the inductor exceeds a selected level as taught by Anderson in order of being able to provide a wider range of duty cycle operations, paragraph 033.
Regarding claim 10, Oi fails to disclose wherein the outermost low-side power FET is controlled by a driver circuit powered by a reduced gate drive circuit configured to selectively set the outer-most low-side power FET to a full gate-drive mode or to a current-limiting reduced gate-drive mode.
Anderson [e.g. Fig. 4] teaches wherein the outermost low-side power FET [e.g. lowest MOSFET directly connected to ground (Inverse of S1)] is controlled by a driver circuit [e.g. 417] powered by a reduced gate drive circuit [e.g. 415] configured to selectively set the outer-most low-side power FET to a full gate-drive mode [e.g. ON] or to a current-limiting reduced gate-drive mode [e.g. OFF].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Oi by wherein the outermost low-side power FET is controlled by a driver circuit powered by a reduced gate drive circuit configured to selectively set the outer-most low-side power FET to a full gate-drive mode or to a current-limiting reduced gate-drive mode as taught by Anderson in order of being able to provide a wider range of duty cycle operations, paragraph 033.
Regarding claim 13, Oi fails to disclose further including a first sensor coupled to the M-level converter cell and configured to toggle the innermost low-side power FET from an ON state to an OFF state if current through the inductor exceeds a selected level.
Anderson [e.g. Fig. 4] teaches further including a first sensor [e.g. 410, 411]coupled to the M-level converter cell and configured to toggle the innermost low-side power FET [e.g. lower S2] from an ON state to an OFF state if current through the inductor exceeds a selected level [e.g. Fig. 6; see inverse of U1 and U2] if current through the inductor exceeds a selected level [e.g. see Fig. 6 with respect to signal inversed U1, U2 at and after time point 604. Paragraph 044 recites “At a second time point 604, the peak of the inductor current has been found by the inductor current matching or exceeding the peak current reference waveform 601”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Oi by further including a first sensor coupled to the M-level converter cell and configured to toggle the innermost low-side power FET from an ON state to an OFF state if current through the inductor exceeds a selected level as taught by Anderson in order of being able to provide a wider range of duty cycle operations, paragraph 033.
Regarding claim 15, Oi fails to disclose wherein the outermost low-side power FET is controlled by a driver circuit powered by a reduced gate drive circuit configured to selectively set the outer-most low-side power FET to a full gate-drive mode or to a current-limiting reduced gate-drive mode.
Anderson [e.g. Fig. 4] teaches wherein the outermost low-side power FET [e.g. lowest MOSFET directly connected to ground (Inverse of S1)] is controlled by a driver circuit [e.g. 417] powered by a reduced gate drive circuit [e.g. 415] configured to selectively set the outer-most low-side power FET to a full gate-drive mode [e.g. ON] or to a current-limiting reduced gate-drive mode [e.g. OFF].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Oi by wherein the outermost low-side power FET is controlled by a driver circuit powered by a reduced gate drive circuit configured to selectively set the outer-most low-side power FET to a full gate-drive mode or to a current-limiting reduced gate-drive mode as taught by Anderson in order of being able to provide a wider range of duty cycle operations, paragraph 033.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claims 4, 9 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 4 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further including sensing current through the inductor and preventing any low-side power FETs from toggling from an OFF state to an ON state until current flow through the inductor is close to zero”.
The primary reason for the indication of the allowability of claim 9 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further including a second sensor coupled to the M-level converter cell and configured to prevent any low-side power FETs from toggling from an OFF state to an ON state until current flow through the inductor is close to zero”.
The primary reason for the indication of the allowability of claim 14 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further including a second sensor coupled to the M-level converter cell and configured to prevent any low-side power FETs from toggling from further including a second sensor coupled to the M-level converter cell and configured to prevent the innermost low-side power FET from toggling from an OFF state to an ON state until current flow through the inductor is close to zero”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838