Prosecution Insights
Last updated: October 02, 2026
Application No. 18/535,731

IMAGE SENSOR AND MANUFACTURING METHOD THEREOF

Final Rejection §102
Filed
Dec 11, 2023
Priority
Jan 13, 2023 — RE 10-2023-0005165
Examiner
HENRY, CALEB E
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Electronics and Telecommunications Research Institute
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
1093 granted / 1259 resolved
+18.8% vs TC avg
Moderate +6% lift
Without
With
+6.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
36 currently pending
Career history
1294
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
55.0%
+15.0% vs TC avg
§102
35.1%
-4.9% vs TC avg
§112
5.9%
-34.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1259 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 7/7/2026 have been fully considered but they are not persuasive. Amendment to independent claims 1 and 7 adds: Claim 1: “…wherein the first germanium pattern having the first conductivity type directly contacts the silicon substrate having the first conductivity type.” Claim 7: “…wherein the first germanium pattern having the first conductivity type directly contacts the silicon substrate having the first conductivity type…” Examiner disagrees that this amendment distinguishes claim 1 and 7 from previously used prior art Hung. In Hung, the first germanium pattern (fig. 4B: 308) having the first conductivity type is separated from the silicon substrate (fig. 4B: 110) having the first conductivity type by silicon liner 32 (please note that layer 21 is a heavily doped part of silicon substrate 110, having the first conductivity). However, par. 39 of Hung makes clear that liner 32 is optional and thus not necessary. Thus, the embodiment of Hung used to reject newly amended claims 1 and 7 is an embodiment wherein liner 32 is absent. In this embedment of Hung, the first germanium pattern (308) having the first conductivity type directly contacts the silicon substrate (110), specifically the heavily doped portion of 110 (i.e. layer 21), having the first conductivity type. Thus, Hung still teaches newly amended claims 1 and 7. For at least this reason, rejection will be made final. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung (20230369360) PNG media_image1.png 546 727 media_image1.png Greyscale Regarding claim 1, Hung teaches a image sensor comprising: a silicon substrate (fig. 4B: 110; par. 32) having a first conductivity type (par. 32); and a read out integrated circuit (ROIC) (fig. 4B: 630 and 640) and a photodetector (please see photodetector in photodetector region 510) on the silicon substrate, wherein the ROIC and the photodetector are spaced apart from each other in a first direction parallel to a top surface of the silicon substrate (see spacing between region 410 and 520 in fig. 4B above), the photodetector comprises a first germanium pattern (fig. 4B: 308) having the first conductivity type (par. 42-44 and 53) and a semiconductor pattern (fig. 4B: 302) having a second conductivity type different from the first conductivity type (par. 53), which are laminated in a direction perpendicular to the top surface of the silicon substrate (please see alignment of 32 and 40), and the first germanium pattern contacts the silicon substrate (please see fig. 4B above), and wherein the first germanium pattern having the first conductivity type directly contacts the silicon substrate having the first conductivity type (please see explanation in Arguments above). Regarding claim 2, Hung teaches a image sensor of claim 1, wherein the semiconductor pattern is a germanium pattern, and the semiconductor pattern contacts the first germanium pattern (par. 53). Regarding claim 3, Hung teaches a image sensor of claim 1, wherein the photodetector further comprises a second germanium pattern disposed between the first germanium pattern and the semiconductor pattern, the second germanium pattern contacts the first germanium pattern and the semiconductor pattern, and the semiconductor pattern is a silicon pattern (par. 41). Regarding claim 4, Hung teaches a image sensor of claim 1, further comprising an intrinsic silicon layer (32; par. 39) disposed on the silicon substrate, wherein the ROIC is disposed at an upper portion of the silicon layer. Regarding claim 5, Hung teaches a image sensor of claim 4, wherein the silicon layer comprises a trench configured to expose the top surface of the silicon substrate, and the photodetector is disposed in the trench (please see fig. 4B above). Regarding claim 6, Hung teaches a image sensor of claim 1, further comprising a line layer (80) disposed on the ROIC and the photodetector. Regarding claim 7, Hung teaches a image sensor comprising: a silicon substrate (110) having a first conductivity type (par. 32); an intrinsic silicon layer (32; par. 39) disposed on the silicon substrate, wherein the silicon layer comprises a trench (please see fig. 4B above) passing through the silicon layer; a read out integrated circuit (ROIC) (630 and 640) disposed at an upper portion of the silicon layer; a photodetector (see fig. 4B above) and a buried insulation pattern (20) disposed in the trench; and metal lines (80) disposed on the photodetector and the ROIC, wherein the photodetector comprises a first germanium pattern (308) having a first conductivity type and a semiconductor pattern (302) having a second conductivity type different from the first conductivity type, which are vertically laminated with each other (please see fig. 4B), wherein the first germanium pattern having the first conductivity type directly contacts the silicon substrate having the first conductivity type (please see explanation in Arguments above), and wherein the buried insulation pattern is disposed between the photodetector and the silicon layer to expose a top surface of the silicon substrate (please see fig. 4B above). Regarding claim 8, Hung teaches a image sensor of claim 7, wherein the semiconductor pattern is a germanium pattern, and the semiconductor pattern contacts the first germanium pattern (par. 53). Regarding claim 9, Hung teaches a image sensor of claim 7, wherein the photodetector further comprises a second germanium pattern disposed between the first germanium pattern and the semiconductor pattern, the second germanium pattern contacts the first germanium pattern and the semiconductor pattern, and the semiconductor pattern is a silicon pattern (par. 41). Regarding claim 10, Hung teaches a image sensor of claim 7, further comprising a mask pattern disposed on the silicon layer, wherein the mask pattern comprises an opening that vertically overlaps the trench (par. 56 and 57). Regarding claim 11, Hung teaches a image sensor of claim 10, wherein each of the mask pattern and the buried insulation pattern comprises a silicon oxide (par. 56 and 57). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CALEB E HENRY/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Dec 11, 2023
Application Filed
Apr 09, 2026
Non-Final Rejection mailed — §102
Jul 07, 2026
Response Filed
Sep 22, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
93%
With Interview (+6.0%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1259 resolved cases by this examiner. Grant probability derived from career allowance rate.

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